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ORCIDDavide Zoni
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2020 – today
- 2020
[j15]Davide Zoni
, Andrea Galimberti, William Fornaciari:
Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials. IEEE Access 8: 75809-75821 (2020)- [j14]Davide Zoni, Andrea Galimberti, William Fornaciari:
Efficient and Scalable FPGA-Oriented Design of QC-LDPC Bit-Flipping Decoders for Post-Quantum Cryptography. IEEE Access 8: 163419-163433 (2020) - [j13]Davide Zoni, Luca Cremona, William Fornaciari:
All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs. IEEE Embed. Syst. Lett. 12(1): 17-20 (2020) - [j12]Davide Zoni, Luca Cremona, William Fornaciari:
All-Digital Control-Theoretic Scheme to Optimize Energy Budget and Allocation in Multi-Cores. IEEE Trans. Computers 69(5): 706-721 (2020) - [j11]Alessandro Barenghi, William Fornaciari, Gerardo Pelosi, Davide Zoni:
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1778-1791 (2020) - [c27]Alessandro Barenghi, Matteo Brevi, William Fornaciari, Gerardo Pelosi, Davide Zoni:
Integrating Side Channel Security in the FPGA Hardware Design Flow. COSADE 2020: 275-290 - [c26]Luca Cremona, William Fornaciari, Andrea Galimberti, Andrea Romanoni, Davide Zoni:
VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer Graphics and Machine Learning Applications. SAMOS 2020: 323-335
2010 – 2019
- 2019
- [c25]Alessandro Barenghi, William Fornaciari, Andrea Galimberti, Gerardo Pelosi, Davide Zoni:
Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions. ICECS 2019: 739-742 - [c24]Tamer Ahmed Eltaras, William Fornaciari, Davide Zoni:
Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-Coherent NoCs. PDP 2019: 33-40 - [c23]Davide Zoni:
Analysis and countermeasures to side-channel attacks: a hardware design perspective. ReCoSoC 2019: 1-4 - 2018
- [j10]José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni:
Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocess. Microsystems 61: 154-170 (2018) - [j9]Davide Zoni, Luca Cremona, Alessandro Cilardo, Mirko Gagliardi, William Fornaciari:
PowerTap: All-digital power meter modeling for run-time power monitoring. Microprocess. Microsystems 63: 128-139 (2018) - [j8]Davide Zoni, Luca Colombo, William Fornaciari:
DarkCache: Energy-Performance Optimization of Tiled Multi-Cores by Adaptively Power-Gating LLC Banks. ACM Trans. Archit. Code Optim. 15(2): 21:1-21:26 (2018) - [j7]Davide Zoni, Alessandro Barenghi, Gerardo Pelosi, William Fornaciari:
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture. ACM Trans. Design Autom. Electr. Syst. 23(5): 57:1-57:30 (2018) - [c22]Giuseppe Massari, Federico Terraneo, Michele Zanella, Davide Zoni:
Towards Fine-Grained DVFS in Embedded Multi-core CPUs. ARCS 2018: 239-251 - [c21]Davide Zoni, Luca Cremona, William Fornaciari:
PowerProbe: Run-time power modeling through automatic RTL instrumentation. DATE 2018: 743-748 - [c20]Michail Noltsis, Panayiotis Englezakis, Eleni Maragkoudaki, Chrysostomos Nicopoulos, Dimitrios Rodopoulos, Francky Catthoor, Yiannakis Sazeides, Davide Zoni, Dimitrios Soudris:
Fast Estimations of Failure Probability Over Long Time Spans. NANOARCH 2018: 1-6 - [c19]William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farres, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni:
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. SAMOS 2018: 187-194 - 2017
- [j6]Davide Zoni, Andrea Canidio, William Fornaciari, Panayiotis Englezakis, Chrysostomos Nicopoulos, Yiannakis Sazeides:
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers. J. Parallel Distributed Comput. 104: 130-145 (2017) - [j5]Kim Grüttner, Ralph Görgen, Sören Schreiner, Fernando Herrera, Pablo Peñil, Julio L. Medina, Eugenio Villar, Gianluca Palermo, William Fornaciari, Carlo Brandolese, Davide Gadioli, Emanuele Vitali, Davide Zoni, Sara Bocchio, Luca Ceva, Paolo Azzoni, Massimo Poncino, Sara Vinco, Enrico Macii, Salvatore Cusenza, John M. Favaro, Raúl Valencia, Ingo Sander, Kathrin Rosvall, Nima Khalilzad, Davide Quaglia:
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties. Microprocess. Microsystems 51: 39-55 (2017) - [c18]Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni:
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. DSD 2017: 478-485 - [c17]Luca Cremona, William Fornaciari, Andrea Marchese, Michele Zanella, Davide Zoni:
DENA: A DVFS-Capable Heterogeneous NoC Architecture. ISVLSI 2017: 489-494 - 2016
- [j4]Davide Zoni, Jose Flich, William Fornaciari:
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-Based NoCs. IEEE Trans. Parallel Distributed Syst. 27(6): 1603-1616 (2016) - [j3]Davide Zoni, Federico Terraneo, William Fornaciari:
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations. J. Signal Process. Syst. 83(3): 357-371 (2016) - [c16]Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni:
Enabling HPC for QoS-sensitive applications: The MANGO approach. DATE 2016: 702-707 - 2015
- [j2]Davide Zoni, William Fornaciari:
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators. ACM J. Emerg. Technol. Comput. Syst. 12(3): 27:1-27:24 (2015) - [j1]Davide Zoni, Federico Terraneo, William Fornaciari:
A control-based methodology for power-performance optimization in NoCs exploiting DVFS. J. Syst. Archit. 61(5-6): 197-209 (2015) - [c15]Jose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, Davide Zoni:
The MANGO FET-HPC Project: An Overview. CSE 2015: 351-354 - [c14]Davide Zoni, Luca Borghese, Giuseppe Massari, Simone Libutti, William Fornaciari:
TEST: Assessing NoC Policies Facing Aging and Leakage Power. DSD 2015: 606-613 - [c13]Federico Terraneo, Davide Zoni, William Fornaciari:
An accurate simulation framework for thermal explorations and optimizations. RAPIDO@HiPEAC 2015: 5:1-5:6 - 2013
- [c12]Davide Zoni, William Fornaciari:
Sensor-wise methodology to face NBTI stress of NoC buffers. DATE 2013: 1038-1043 - [c11]Davide Zoni, William Fornaciari:
NBTI-aware design of NoC buffers. INA-OCMC@HiPEAC 2013: 25-28 - [c10]Federico Terraneo, Davide Zoni, William Fornaciari:
A cycle accurate simulation framework for asynchronous NoC design. ISSoC 2013: 1-8 - [c9]Davide Zoni, Jose Flich, William Fornaciari:
Adaptive routing and Dynamic Frequency Scaling for NoC power-performance optimizations. PATMOS 2013: 231-234 - [c8]Davide Zoni, Federico Terraneo, William Fornaciari:
An analytical, dynamic, power-performance router model for run-time NoC optimizations. SoCC 2013: 290-295 - 2012
- [c7]Davide Zoni, Patrick Bellasi, William Fornaciari:
A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures. ARCS 2012: 86-97 - [c6]Andrea Sansottera, Davide Zoni, Paolo Cremonesi, William Fornaciari:
Consolidation of multi-tier workloads with performance and reliability constraints. HPCS 2012: 74-83 - [c5]Davide Zoni, Simone Corbetta, William Fornaciari:
HANDS: heterogeneous architectures and networks-on-chip design and simulation. ISLPED 2012: 261-266 - [c4]Davide Zoni, Simone Corbetta, William Fornaciari:
Thermal/performance trade-off in network-on-chip architectures. ISSoC 2012: 1-8 - [c3]Simone Corbetta, Davide Zoni, William Fornaciari:
A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures. ISVLSI 2012: 51-56 - [c2]Carlo Brandolese, William Fornaciari, Luigi Rucco, Davide Zoni:
Towards energy-efficient functional configuration in WSNs. PDeS 2012: 37-42 - [c1]Davide Zoni, William Fornaciari:
A sensor-less NBTI mitigation methodology for NoC architectures. SoCC 2012: 340-345
Coauthor Index
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