Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDCASES 2003: San Jose, California, USA
- Jaime H. Moreno, Praveen K. Murthy, Thomas M. Conte, Paolo Faraboschi:
Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003. ACM 2003, ISBN 1-58113-676-5 - Joseph A. Fisher:
Moving from embedded systems to embedded computing. 1
Compilation
- Dorit Naishlos, Marina Biberstein, Shay Ben-David, Ayal Zaks:
Vectorizing for a SIMdD DSP architecture. 2-11 - Bengu Li, Rajiv Gupta:
Simple offset assignment in presence of subword data. 12-23 - V. Krishna Nandivada, Jens Palsberg:
Efficient spill code for SDRAM. 24-31 - Andrei Sergeevich Terechko
, Erwan Le Thenaff, Henk Corporaal:
Cluster assignment of global values for clustered VLIW processors. 32-40
Task Scheduling and Real-Time
- Benjamin J. Welch, Shobhit O. Kanaujia, Adarsh Seetharam, Deepaksrivats Thirumalai, Alexander G. Dean:
Extending STI for demanding hard-real-time systems. 41-50 - Andreas Ermedahl, Friedhelm Stappert, Jakob Engblom:
Clustered calculation of worst-case execution times. 51-62 - Peter Poplavko, Twan Basten, Marco Bekooij, Jef L. van Meerbergen, Bart Mesman:
Task-level timing models for guaranteed performance in multiprocessor networks-on-chip. 63-72 - Juanjo Noguera, Rosa M. Badia:
System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures. 73-83
Code Compression
- Jeremy Lau, Stefan Schoenmackers, Timothy Sherwood, Brad Calder:
Reducing code size with echo instructions. 84-94 - Montserrat Ros, Peter Sutton:
Compiler optimization and ordering effects on VLIW code compression. 95-103 - Partha Biswas, Nikil D. Dutt:
Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. 104-112 - Krishna V. Palem:
Energy aware algorithm design via probabilistic computing: from algorithms and models to Moore's law and novel (semiconductor) devices. 113-116
Microprocessor Architecture
- Ann Gordon-Ross, Frank Vahid:
Frequent loop detection using efficient non-intrusive on-chip hardware. 117-124 - Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown:
Increasing the number of effective registers in a low-power processor using a windowed register file. 125-136 - David Goodwin, Darin Petkov:
Automatic generation of application specific processors. 137-147 - Osvaldo Colavin, Davide Rizzo:
A scalable wide-issue clustered VLIW with a reconfigurable interconnect. 148-158
Emerging Areas
- Hillery C. Hunter, Jaime H. Moreno:
A new look at exploiting data parallelism in embedded systems. 159-169 - Massimo Baleani, Alberto Ferrari, Leonardo Mangeruca, Alberto L. Sangiovanni-Vincentelli, Maurizio Peri, Saverio Pezzini:
Fault-tolerant platforms for automotive safety-critical applications. 170-177 - Chidamber Kulkarni, Matthias Gries, Christian Sauer, Kurt Keutzer:
Programming challenges in network processor deployment. 178-187
Embedded Applications
- Ramnath Venugopalan, Prasanth Ganesan, Pushkin Peddabachagari, Alexander G. Dean, Frank Mueller, Mihail L. Sichitiu:
Encryption overhead in embedded systems and sensor network nodes: modeling and analysis. 188-197 - Dino Oliva, Rainer Buchty, Nevin Heintze:
AES and the cryptonite crypto processor. 198-209 - Binu K. Mathew, Al Davis, Zhen Fang:
A low-power accelerator for the SPHINX 3 speech recognition system. 210-219 - Rajeev Krishna, Scott A. Mahlke, Todd M. Austin:
Architectural optimizations for low-power, real-time speech recognition. 220-231
Power and Energy
- Lin Zhong, Niraj K. Jha:
Graphical user interface energy characterization for handheld computers. 232-242 - Sumit Mohanty, Viktor K. Prasanna:
A hierarchical approach for energy efficient application design using heterogeneous embedded systems. 243-254 - Ankush Varma, Brinda Ganesh, Mainak Sen, Suchismita Roy Choudhury, Lakshmi Srinivasan, Bruce L. Jacob:
A control-theoretic approach to dynamic voltage scheduling. 255-266 - Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan:
Power efficient encoding techniques for off-chip data buses. 267-275
Memory Hierarchy
- Sumesh Udayakumaran, Rajeev Barua:
Compiler-decided dynamic memory allocation for scratch-pad based embedded systems. 276-286 - Guilin Chen, Mahmut T. Kandemir, Hendra Saputra, Mary Jane Irwin:
Exploiting bank locality in multi-bank memories. 287-297 - Alain Darte, Robert Schreiber, Gilles Villard:
Lattice-based memory allocation. 298-308 - Wei Zhang, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin:
Performance, energy, and reliability tradeoffs in replicating hot cache lines. 309-317 - Federico Angiolini, Luca Benini, Alberto Caprara:
Polynomial-time algorithm for on-chip scratchpad memory partitioning. 318-326
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-25 05:27 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
