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ORCID4th FCCM 1996: Napa, CA, USA
- 4th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM '96), Napa Valley, CA, USA, April 17-19, 1996. IEEE 1996, ISBN 0-8186-7548-9
- Roger F. Woods, A. Cassidy, J. Gray:
VLSI architectures for field programmable gate arrays: a case study. 2-9 - Bernard K. Gunther, George Milne, V. Lakshmi Narasimhan:
Assessing document relevance with run-time reconfigurable machines. 10-17 - William E. King IV, Thomas H. Drayer, Richard W. Conners, Philip A. Araman:
Using MORRPH in an industrial machine vision system. 18-26 - Alan S. Wenban, Geoffrey Brown:
A software development system for FPGA-based data acquisition systems. 28-37 - Tsuyoshi Isshiki, Wayne Wei-Ming Dai:
Bit-serial pipeline synthesis for multi-FPGA systems with C++ design capture. 38-47 - Bernard Pottier, José-Luis Llopis:
Revisiting Smalltalk-80 blocks: a logic generator for FPGAs. 48-57 - David Yeh, Gennady Feygin, Paul Chow:
RACER: a reconfigurable constraint-length 14 Viterbi decoder. 60-69 - John D. Villasenor, Brian Schoner, Kang-Ngee Chia, Charles Zapata, Hea Joung Kim, Christopher R. Jones, Shane Lansing, Bill Mangione-Smith:
Configurable computing solutions for automatic target recognition. 70-79 - W. Bruce Culbertson, Rick Amerson, Richard J. Carter, Philip Kuekes, Greg Snider:
Exploring architectures for volume visualization on the Teramac custom computer. 80-88 - Peter M. Athanas, Rhett Daniel Hudson:
Using rapid prototyping to teach the design of complete computing solutions. 90-97 - Yamin Li, Wanming Chu:
Aizup-a pipelined processor design and implementation on XILINX FPGA chip. 98-106 - Loucas Louca, Todd A. Cook, William H. Johnson:
Implementation of IEEE single precision floating point addition and multiplication on FPGAs. 107-116 - Pieter J. Bakkes, Jan J. Du Plessis, Brad L. Hutchings:
Mixing fixed and reconfigurable logic for array processing. 118-125 - Ralph Wittig, Paul Chow:
OneChip: an FPGA processor with reconfigurable logic. 126-135 - Günter Knittel:
A PCI-compatible FPGA-coprocessor for 2D/3D image processing. 136-145 - Tsukasa Yamauchi, Shogo Nakaya, Nobuki Kajihara:
SOP: a reconfigurable massively parallel system and its control-data-flow based compiling method. 148-156 - Ethan Mirsky, André DeHon:
MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources. 157-166 - Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung:
Modelling and optimising run-time reconfigurable systems. 167-176 - James B. Peterson, R. Brendan O'Connor, Peter M. Athanas:
Scheduling and partitioning ANSI-C programs onto multi-FPGA CCM architectures. 178-187 - Satnam Singh, Jonathan Hogg, Derek McAuley:
Expressing dynamic reconfiguration by partial evaluation. 188-194 - David A. Clark, Brad L. Hutchings:
Supporting FPGA microprocessors through retargetable software tools. 195-203 - Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke:
On the viability of FPGA-based integrated coprocessors. 206-215 - Paul S. Graham, Brent E. Nelson:
Genetic algorithms in software and in hardware-a performance analysis of workstation and custom computing machine implementations. 216-225 - Sriram K. Rajamani, Pramod Viswanath:
A quantitative analysis of processor-programmable logic interface. 226-234
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