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ORCID9th FCCM 2001: Rohnert Park, California, USA
- The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001, Rohnert Park, California, USA, April 29 - May 2, 2001. IEEE Computer Society 2001, ISBN 0-7695-2667-5
DSP
- Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prith Banerjee:
Parallelization of MATLAB Applications for a Multi-FPGA System. 1-9 - Sze-Wei Ong, Nabil Kerkiz, Bernadeta Srijanto, Chandra Tan, Michael A. Langston, Danny F. Newport, Donald W. Bouldin:
Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems. 10-20 - Monk-Ping Leong, Craig T. Jin, Philip Heng Wai Leong:
Parameterized Module Generator for an FPGA-Based Electronic Cochlea. 21-30
Tools
- João M. P. Cardoso:
Novel Algorithm Combining Temporal Partitioning and Sharing of Functional Units. 31-40 - Paul S. Graham, Brent E. Nelson, Brad L. Hutchings:
Instrumenting Bitstreams for Debugging FPGA Circuits. 41-50
Arithmetic
- George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
The Multiple Wordlength Paradigm. 51-60 - Zhijun Huang, Milos D. Ercegovac:
FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization. 61-70 - Ranjani Parthasarathi, Easwaran Raman, Karthik Sankaranarayanan, Lakshmi N. Chakrapani:
A Reconfigurable Co-Processor for Variable Long Precision Arithmetic Using Indian Algorithms. 71-80
JBits
- Philip James-Roxby, Daniel J. Downs:
An Efficient Content-Addressable Memory Implementation Using Dynamic Routing. 81-90 - Satnam Singh, Philip James-Roxby:
Lava and JBits: From HDL to Bitstream in Seconds. 91-100
Architecture I
- Apostolos Dollas, Dionisios N. Pnevmatikatos, Nikolaos Aslanides, Stamatios Kavvadias, Euripides Sotiriades, Sotirios Zogopoulos, Kyprianos Papademetriou, Grigorios Chrysos, Konstantinos Harteros, Emanouil Antonidakis, Nikolaos Petrakis:
Architecture and Application of PLATO, A Reconfigurable Active Network Platform. 101-110 - Katherine Compton, Scott Hauck:
Totem: Custom Reconfigurable Array Generation. 111-119 - Tomoyoshi Kobori, Tsutomu Maruyama, Tsutomu Hoshino:
A Cellular Automata System with FPGA. 120-129
Fault Tolerance
- Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi:
A Fault-Tolerance Scheme for a MIN-Based Multi-Sensor System. 130-136 - Wei-Je Huang, Edward J. McCluskey:
Column-Based Precompiled Configuration Techniques for FPGA. 137-146
Architecture II
- Zhiyuan Li, Scott Hauck:
Configuration Compression for Virtex FPGAs. 147-159 - Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers:
An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia. 160-169 - Philip Heng Wai Leong, Monk-Ping Leong, Ocean Y. H. Cheung, T. Tung, C. M. Kwok, Ming Yiu Wong, Kin-Hong Lee:
Pilchard - A Reconfigurable Computing Platform with Memory Slot Interface. 170-179
Applications I
- Keith D. Underwood, Ron R. Sass, Walter B. Ligon III:
Acceleration of a 2D-FFT on an Adaptable Computing Cluster. 180-189 - Abdsamad Benkrid, Danny Crookes, Khaled Benkrid:
Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGA. 190-198
Image Processing
- K. Scott Hemmert, Brad L. Hutchings, Anshul Malvi:
An Application-Specific Compiler for High-Speed Binary Image Morphology. 199-208 - A. P. Wim Böhm, Bruce A. Draper, Walid A. Najjar, Jeffrey Hammes, Robert Rinker, Monica Chawathe, Charlie Ross:
One-Step Compilation of Image Processing Applications to FPGAs. 209-218 - Khaled Benkrid, Danny Crookes, J. Smith, Abdsamad Benkrid:
High Level Programming for FPGA Based Image and Video Processing Using Hardware Skeletons. 219-226
Applications II
- Reetinder P. S. Sidhu, Viktor K. Prasanna:
Fast Regular Expression Matching Using FPGAs. 227-238 - José T. de Sousa, J. M. da Silva, Miron Abramovici:
A Configurable Hardware/Software Approach to SAT Solving. 239-248
Posters
- Grant B. Wigley, David A. Kearney:
The Development of an Operating System for Reconfigurable Computing. 249-250 - Cameron Patterson, Steven A. Guccione:
JBits™ Design Abstractions. 251-252 - Pedro C. Diniz, Ashok Venkatachar:
A Behavioral Synthesis Estimation Interface for Configurable Computing. 253-254 - Tsutomu Maruyama:
An Approach for Automatic Data Allocation in C to HDL Compilers. 255-256 - Sakir Sezer, Eimear Stewart, Marc Carson, Claire Greenwood:
System on a FPGA Virtual Concatenation. 257-258 - Tom Kean:
Secure Configuration of a Field Programmable Gate Array. 259-260 - Gordon J. Brebner
, Irwin Kennedy:
Circlets: Circuitry over the Internet. 261-262 - Abhishek Singhal, Arun K. Somani, Akhilesh Tyagi:
Evaluation of Reconfigurable Cache Module Architecture. 263-266 - Joonseok Park, Pedro C. Diniz:
An External Memory Interface for FPGA-Based Computing Engines. 267-268 - Yajun Ha, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man:
A SW/HW Interface API for Java/FPGA Co-Designed Applets. 269-270 - Klaus Kornmesser, Andreas Kugel, Reinhard Männer:
The FPGA Development System CHDL. 271-272 - Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay:
Combining Instruction and Loop Level Parallelism for FPGAs. 273-282 - Yan Solihin, Kirk W. Cameron, Yong Luo, Dominique Lavenier, Maya B. Gokhale:
Mutable Functional Units: Initial Results. 283-284 - Kenneth Mackenzie, Adam Johnson:
Rapid Synthesis of Pattern Classification Circuits. 285-286 - Jörn Gause, Carsten Reuter, Holger Kropp, Peter Y. K. Cheung, Wayne Luk:
The Effect of FPGA Granularity on Video Codec Implementations. 287-288 - Francisco Ibarra Picó, Sergio Cuenca-Asensi, Víctor Córcoles López:
Accelerating Statistical Texture Analysis with an FPGA-DSP Hybrid Architecture. 289-290 - Wagdy H. Mahmoud, Roger L. Haggard, Mohamed Abdelrahman:
Hardware Implementation of Automated Sensor Self-Validation System for Cupola Furnaces. 291-299 - Tim Todman, Wayne Luk:
Reconfigurable Designs for Ray Tracing. 300-301 - J. Patel, V. Prabhu:
Manufacturing Shop-Floor Supercomputer for Distributed Simulation and Control. 302-303 - Nicolas Boullis, Oskar Mencer, Wayne Luk, Henry Styles:
Pipelined Function Evaluation on FPGAs. 304-306 - Pawel J. Rajda:
Optimization of Logic Use on Stereo Vision Algorithm Example. 307-308
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