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Prithviraj Banerjee
Prith Banerjee
Person information
- affiliation: Northwestern University, Illinois, USA
- award (1987): Presidential Young Investigator Award
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2020 – today
- 2024
- [i3]Prithviraj Banerjee, Sindi Shkodrani, Pierre Moulon, Shreyas Hampali, Fan Zhang, Jade Fountain, Edward Miller, Selen Basol, Richard A. Newcombe, Robert Wang, Jakob Julian Engel, Tomas Hodan:
Introducing HOT3D: An Egocentric Dataset for 3D Hand and Object Tracking. CoRR abs/2406.09598 (2024) - [i2]Prithviraj Banerjee, Sindi Shkodrani, Pierre Moulon, Shreyas Hampali, Shangchen Han, Fan Zhang, Linguang Zhang, Jade Fountain, Edward Miller, Selen Basol, Richard A. Newcombe, Robert Wang, Jakob Julian Engel, Tomas Hodan:
HOT3D: Hand and Object Tracking in 3D from Egocentric Multi-View Videos. CoRR abs/2411.19167 (2024) - 2022
- [j82]Matt Adams
, Xiao Li, Lucas Boucinha, Sameer S. Kher, Prith Banerjee, Jose-Luis Gonzalez:
Hybrid Digital Twins: A Primer on Combining Physics-Based and Data Analytics Approaches. IEEE Softw. 39(2): 47-52 (2022) - [c213]Jiuhong Xiao
, Lavisha Aggarwal, Prithviraj Banerjee, Manoj Aggarwal, Gerard Medioni:
Identity Preserving Loss for Learned Image Compression. CVPR Workshops 2022: 516-525 - [i1]Jiuhong Xiao, Lavisha Aggarwal, Prithviraj Banerjee, Manoj Aggarwal, Gerard Medioni:
Identity Preserving Loss for Learned Image Compression. CoRR abs/2204.10869 (2022)
2010 – 2019
- 2014
- [c212]Prithviraj Banerjee, Ram Nevatia:
Multi-state Discriminative Video Segment Selection for Complex Event Classification. ACCV (5) 2014: 162-177 - [c211]Prithviraj Banerjee, Ramakant Nevatia:
Pose Filter Based Hidden-CRF Models for Activity Detection. ECCV (2) 2014: 711-726 - 2012
- [j81]Prithviraj Banerjee, Chandrakant D. Patel, Cullen E. Bash
, Amip Shah, Martin F. Arlitt:
Towards a net-zero data center. ACM J. Emerg. Technol. Comput. Syst. 8(4): 27:1-27:39 (2012) - [j80]Pramod G. Joisha, Robert S. Schreiber, Prithviraj Banerjee, Hans-Juergen Boehm, Dhruva R. Chakrabarti:
On a Technique for Transparently Empowering Classical Compiler Optimizations on Multithreaded Code. ACM Trans. Program. Lang. Syst. 34(2): 9:1-9:42 (2012) - [c210]Prithviraj Banerjee, Ramakant Nevatia:
Pose based activity recognition using Multiple Kernel learning. ICPR 2012: 445-448 - 2011
- [j79]Prith Banerjee, Rich Friedrich, Cullen E. Bash
, Patrick Goldsack, Bernardo A. Huberman, John Manley, Chandrakant D. Patel, Parthasarathy Ranganathan, Alistair C. Veitch:
Everything as a Service: Powering the New Information Economy. Computer 44(3): 36-43 (2011) - [c209]Lei Gao, Gaurav Mittal, David Zaretsky, Prith Banerjee:
Resource optimization and deadlock prevention while generating streaming architectures from ordinary programs. AHS 2011: 9-16 - [c208]Prithviraj Banerjee, Ram Nevatia:
Learning neighborhood cooccurrence statistics of sparse features for human activity recognition. AVSS 2011: 212-217 - [c207]Dhruva R. Chakrabarti, Prithviraj Banerjee, Hans-Juergen Boehm, Pramod G. Joisha, Robert S. Schreiber:
The runtime abort graph and its application to software transactional memory optimization. CGO 2011: 42-53 - [c206]Pramod G. Joisha, Robert S. Schreiber, Prithviraj Banerjee, Hans-Juergen Boehm, Dhruva R. Chakrabarti:
A technique for the effective and automatic reuse of classical compiler optimizations on multithreaded code. POPL 2011: 623-636 - 2010
- [j78]Prith Banerjee, Rich Friedrich, Lueny Morell:
Open Innovation at HP Labs. Computer 43(11): 88-90 (2010) - [c205]Prithviraj Banerjee, Ram Nevatia:
Dynamics Based Trajectory Segmentation for UAV videos. AVSS 2010: 345-352 - [c204]Prith Banerjee:
An Intelligent IT Infrastructure for the Future. ICDCN 2010: 1 - [c203]Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee:
Automatic Generation of Stream Descriptors for Streaming Architectures. ICPP 2010: 307-312 - [c202]Pradeep Natarajan, Prithviraj Banerjee, Ram Nevatia:
Accurate person tracking through changing poses for multi-view action recognition. ICVGIP 2010: 155-161
2000 – 2009
- 2009
- [c201]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. ASP-DAC 2009: 636-641 - [c200]Prith Banerjee, Chandrakant D. Patel, Cullen E. Bash, Parthasarathy Ranganathan:
Sustainable data centers: enabled by supply and demand side management. DAC 2009: 884-887 - [c199]Gaurav Mittal, David Zaretsky, Prithviraj Banerjee:
Streaming implementation of a sequential decompression algorithm on an FPGA. FPGA 2009: 283 - [c198]Prith Banerjee:
An intelligent IT infrastructure for the future. HPCA 2009: 3-4 - [c197]Lei Gao, Gaurav Mittal, David Zaretsky, Dan Schonfeld, Prithviraj Banerjee:
An Automated Algorithm to Generate Stream Programs. ISCAS 2009: 1505-1508 - [c196]David Zaretsky, Gaurav Mittal, Prithviraj Banerjee:
Streaming Implementation of the ZLIB Decoder Algorithm on an FPGA. ISCAS 2009: 2329-2332 - [c195]Lei Gao, David Zaretsky, Gaurav Mittal, Dan Schonfeld, Prith Banerjee:
A software pipelining algorithm in high-level synthesis for FPGA architectures. ISQED 2009: 297-302 - 2008
- [c194]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications. ASP-DAC 2008: 42-48 - [c193]Nikolaos D. Liveris, Hai Zhou, Robert P. Dick, Prithviraj Banerjee:
State space abstraction for parameterized self-stabilizing embedded systems. EMSOFT 2008: 11-20 - 2007
- [j77]Pramod G. Joisha, Prithviraj Banerjee:
A translator system for the MATLAB language. Softw. Pract. Exp. 37(5): 535-578 (2007) - [j76]Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3): 447-455 (2007) - [j75]Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee:
An Overview of a Compiler for Mapping Software Binaries to Hardware. IEEE Trans. Very Large Scale Integr. Syst. 15(11): 1177-1190 (2007) - [c192]Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee:
Retiming for Synchronous Data Flow Graphs. ASP-DAC 2007: 480-485 - [c191]David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs. ISQED 2007: 595-601 - 2006
- [j74]Tianyi Jiang, Xiaoyong Tang, Prith Banerjee:
Macro-models for high-level area and power estimation on FPGAs. Int. J. Simul. Process. Model. 2(1/2): 12-19 (2006) - [j73]Pramod G. Joisha, Prithviraj Banerjee:
An algebraic array shape inference system for MATLAB. ACM Trans. Program. Lang. Syst. 28(5): 848-907 (2006) - [c190]Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. DATE 2006: 618-623 - [c189]David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Dynamic Template Generation for Resource Sharing in Control and Data Flow Graphs. VLSI Design 2006: 465-468 - 2005
- [j72]Xiaoyong Tang, Tianyi Jiang, Alex K. Jones, Prithviraj Banerjee:
High-Level Synthesis for Low Power Hardware Implementation of Unscheduled Data-Dominated Circuits. J. Low Power Electron. 1(3): 259-272 (2005) - [j71]Sanghamitra Roy
, Prith Banerjee:
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design. IEEE Trans. Computers 54(7): 886-896 (2005) - [c188]Gaurav Mittal, David Zaretsky, Gokhan Memik, Prith Banerjee:
Automatic extraction of function bodies from software binaries. ASP-DAC 2005: 928-931 - [c187]Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. Asian Test Symposium 2005: 28-33 - [c186]Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee:
Leakage power optimization with dual-Vth library in high-level synthesis. DAC 2005: 202-207 - [c185]David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee:
Generation of Control and Data Flow Graphs from Scheduled and Pipelined Assembly Code. LCPC 2005: 76-90 - [c184]Xiaoyong Tang, Tianyi Jiang, Alex K. Jones
, Prithviraj Banerjee:
Behavioral Synthesis of Data-Dominated Circuits for Minimal Energy Implementation. VLSI Design 2005: 267-273 - 2004
- [j70]Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Vikram Saxena, Steven Parkes, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, David Zaretsky, Robert Anderson, Juan Ramon Uribe:
Overview of a compiler for synthesizing MATLAB programs onto FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 312-324 (2004) - [c183]Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee:
Automatic translation of software binaries onto FPGAs. DAC 2004: 389-394 - [c182]Sanghamitra Roy
, Prithviraj Banerjee:
An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. DAC 2004: 484-487 - [c181]Nikolaos D. Liveris, Prithviraj Banerjee:
Power Aware Interface Synthesis for Bus-Based SoC Design. DATE 2004: 864-869 - [c180]David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee:
Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. FCCM 2004: 37-46 - [c179]Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee:
High level area, delay and power estimation for FPGAs. FPGA 2004: 249 - [c178]Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee:
An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. FPGA 2004: 256 - [c177]Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee:
Macro-models for high level area and power estimation on FPGAs. ACM Great Lakes Symposium on VLSI 2004: 162-165 - [c176]David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee:
Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. ACM Great Lakes Symposium on VLSI 2004: 397-400 - [c175]Rajarshi Mukherjee, Alex K. Jones
, Prithviraj Banerjee:
Handling Data Streams while Compiling C Programs onto Hardware. ISVLSI 2004: 271-272 - 2003
- [j69]Amitabh Mishra, Prithviraj Banerjee:
An Algorithm-Based Error Detection Scheme for the Multigrid Method. IEEE Trans. Computers 52(9): 1089-1099 (2003) - [j68]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam
, Prithviraj Banerjee:
Reducing False Sharing and Improving Spatial Locality in a Unified Compilation Framework. IEEE Trans. Parallel Distributed Syst. 14(4): 337-354 (2003) - [c174]Robert Reuss, Jose L. Muñoz, Toshiaki Miyazaki, Nader Bagherzadeh, Prith Banerjee, Brad L. Hutchings, Brian Schott:
Adaptive computing: what can it do, where can it go? ASP-DAC 2003: 463 - [c173]Prith Banerjee:
An overview of a compiler for mapping MATLAB programs onto FPGAs. ASP-DAC 2003: 477-482 - [c172]Pramod G. Joisha, Prithviraj Banerjee:
The MAGICA Type Inference Engine for MATLAB. CC 2003: 121-125 - [c171]Prithviraj Banerjee, Debabrata Bagchi, Malay Haldar, Anshuman Nayak, Victor Kim, R. Uribe:
Automatic Conversion of Floating Point MATLAB Programs into Fixed Point FPGA Based Hardware Design. FCCM 2003: 263-264 - [c170]Alex K. Jones
, Prithviraj Banerjee:
An Automated and Power-Aware Framework for Utilization of IP Cores in Hardware Generated from C Descriptions Targeting FPGAs. FCCM 2003: 284-285 - [c169]Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson:
Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. FPGA 2003: 237 - [c168]Alex K. Jones, Prithviraj Banerjee:
An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. FPGA 2003: 244 - [c167]Pramod G. Joisha, Prithviraj Banerjee:
Static array storage optimization in MATLAB. PLDI 2003: 258-268 - 2002
- [j67]Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee:
Automatic Parallelization of Compiled Event Driven VHDL Simulation. IEEE Trans. Computers 51(4): 380-394 (2002) - [c166]Alex K. Jones
, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee:
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. CASES 2002: 188-197 - [c165]Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee:
Accurate Area and Delay Estimators for FPGAs. DATE 2002: 862-869 - [c164]Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi:
A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs. IWDC 2002: 246-256 - 2001
- [j66]Dhruva R. Chakrabarti, Prithviraj Banerjee:
Static Single Assignment Form for Message-Passing Programs. Int. J. Parallel Program. 29(2): 139-184 (2001) - [j65]Yanhong Yuan, Prithviraj Banerjee:
A Parallel Implementation of a Fast Multipole-Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputers. J. Parallel Distributed Comput. 61(12): 1751-1774 (2001) - [j64]Pramod G. Joisha, Abhay Kanhere, Prithviraj Banerjee, U. Nagaraj Shenoy, Alok N. Choudhary:
Handling context-sensitive syntactic issues in the design of a front-end for a MATLAB compiler. ACM SIGAPL APL Quote Quad 31(3): 27-40 (2001) - [j63]Mahmut T. Kandemir, J. Ramanujam
, Alok N. Choudhary, Prithviraj Banerjee:
A Layout-Conscious Iteration Space Transformation Technique. IEEE Trans. Computers 50(12): 1321-1336 (2001) - [j62]U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee:
An algorithm for synthesis of large time-constrained heterogeneous adaptive systems. ACM Trans. Design Autom. Electr. Syst. 6(2): 207-225 (2001) - [j61]Pramod G. Joisha, Prithviraj Banerjee:
The Efficient Computation of Ownership Sets in HPF. IEEE Trans. Parallel Distributed Syst. 12(8): 769-788 (2001) - [j60]Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam
, Eduard Ayguadé
:
Static and Dynamic Locality Optimizations Using Integer Linear Programming. IEEE Trans. Parallel Distributed Syst. 12(9): 922-941 (2001) - [j59]Anshuman Nayak, Malay Haldar, Prith Banerjee, Chunhong Chen, Majid Sarrafzadeh:
Power Optimization of Delay Constrained Circuits. VLSI Design 12(2): 125-138 (2001) - [c163]Pramod G. Joisha, Prithviraj Banerjee:
Correctly detecting intrinsic type errors in typeless languages such as MATLAB. APL 2001: 7-21 - [c162]Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB. ASP-DAC 2001: 645-648 - [c161]Daniel J. Palermo, Eugene W. Hodges IV, Prithviraj Banerjee:
Compiler Optimization of Dynamic Data Distributions for Distributed-Memory Multicomputers. Compiler Optimizations for Scalable Parallel Systems Languages 2001: 445-484 - [c160]Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee:
Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs. DATE 2001: 722-728 - [c159]Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prith Banerjee:
Parallelization of MATLAB Applications for a Multi-FPGA System. FCCM 2001: 1-9 - [c158]Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
A System for Synthesizing Optimized FPGA Hardware from MATLAB. ICCAD 2001: 314-319 - [c157]Dhruva R. Chakrabarti, Prithviraj Banerjee:
Global optimization techniques for automatic parallelization of hybrid applications. ICS 2001: 166-180 - [c156]Pramod G. Joisha, U. Nagaraj Shenoy, Prithviraj Banerjee:
Computing Array Shapes in MATLAB. LCPC 2001: 395-410 - [c155]Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee, U. Nagaraj Shenoy:
Fpga Hardware Synthesis From Matlab. VLSI Design 2001: 299-304 - [c154]U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary, Mahmut T. Kandemir:
Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators. VLSI Design 2001: 305-310 - 2000
- [j58]Antonio Lain, Dhruva R. Chakrabarti, Prithviraj Banerjee:
Compiler and Run-Time Support for Exploiting Regularity within Irregular Applications. IEEE Trans. Parallel Distributed Syst. 11(2): 119-135 (2000) - [j57]Mahmut T. Kandemir, Alok N. Choudhary, Prithviraj Banerjee, J. Ramanujam
, U. Nagaraj Shenoy:
Minimizing Data and Synchronization Costs in One-Way Communication. IEEE Trans. Parallel Distributed Syst. 11(12): 1232-1251 (2000) - [c153]Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
Scheduling algorithms for automated synthesis of pipelined designs on FPGAs for applications described in MATLAB. CASES 2000: 85-93 - [c152]U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary:
A System-Level Synthesis Algorithm with Guaranteed Solution Quality. DATE 2000: 417-424 - [c151]Prithviraj Banerjee, U. Nagaraj Shenoy, Alok N. Choudhary, Scott Hauck, C. Bachmann, Malay Haldar, Pramod G. Joisha, Alex K. Jones
, Abhay Kanhere, Anshuman Nayak, S. Periyacheri, M. Walkden, David Zaretsky:
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems. FCCM 2000: 39-48 - [c150]Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerjee:
A C compiler for a processor with a reconfigurable functional unit. FPGA 2000: 95-100 - [c149]Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
Parallel algorithms for FPGA placement. ACM Great Lakes Symposium on VLSI 2000: 86-94 - [c148]Yanhong Yuan, Prithviraj Banerjee:
Comparative Study of Parallel Algorithms for 3-D Capacitance Extraction on Distributed Memory Multiprocessors. ICCD 2000: 133-138 - [c147]Malay Haldar, Anshuman Nayak, Abhay Kanhere, Pramod G. Joisha, U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee:
Match Virtual Machine: An Adaptive Runtime System to Execute MATLAB in Parallel. ICPP 2000: 145-152 - [c146]Victor Kim, Prithviraj Banerjee, Kaushik De:
Fine-Grained Parallel VLSI Synthesis for Commercial CAD on a Network of Workstations. ICPP 2000: 421-430 - [c145]Yanhong Yuan, Prithviraj Banerjee:
A Parallel Implementation of a Fast Multipole Based 3-D Capacitance Extraction Program on Distributed Memory Multicomputer. IPDPS 2000: 323-330 - [c144]Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithviraj Banerjee:
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. ISCA 2000: 225-235 - [c143]Pramod G. Joisha, Prithviraj Banerjee:
Exploiting Ownership Sets in HPF. LCPC 2000: 259-273 - [e3]Majid Sarrafzadeh, Prithviraj Banerjee, Kaushik Roy:
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, Chicago, Illinois, USA, March 2-4, 2000. ACM 2000, ISBN 1-58113-251-4 [contents]
1990 – 1999
- 1999
- [j56]John A. Chandy
, Prithviraj Banerjee:
A Parallel Circuit-Partitioned Algorithm for Timing-Driven Standard Cell Placement. J. Parallel Distributed Comput. 57(1): 64-90 (1999) - [j55]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam
, Prithviraj Banerjee:
A Matrix-Based Approach to Global Locality Optimization. J. Parallel Distributed Comput. 58(2): 190-235 (1999) - [j54]Pradeep Prabhakaran, Prithviraj Banerjee:
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs. IEEE Trans. Computers 48(7): 762-768 (1999) - [j53]Mahmut T. Kandemir, Prithviraj Banerjee, Alok N. Choudhary, J. Ramanujam
, U. Nagaraj Shenoy:
A global communication optimization technique based on data-flow analysis and linear algebra. ACM Trans. Program. Lang. Syst. 21(6): 1251-1297 (1999) - [j52]Mahmut T. Kandemir, Alok N. Choudhary, U. Nagaraj Shenoy, Prithviraj Banerjee, J. Ramanujam
:
A Linear Algebra Framework for Automatic Determination of Optimal Data Layouts. IEEE Trans. Parallel Distributed Syst. 10(2): 115-135 (1999) - [j51]Maogang Wang, Prithviraj Banerjee, Majid Sarrafzadeh:
Placement with Incomplete Data. VLSI Design 10(1): 57-70 (1999) - [c142]Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee:
On Reducing False Sharing while Improving Locality on Shared Memory Multiprocessors. IEEE PACT 1999: 203-211 - [c141]Sumit Roy, Krishna P. Belkhale, Prithviraj Banerjee:
An Approxmimate Algorithm for Delay-Constraint Technology Mapping. DAC 1999: 367-372 - [c140]Amitabh Mishra, Prithviraj Banerjee:
An Algorithm Based Error Detection Scheme for the Multigrid Algorithm. FTCS 1999: 12-19 - [c139]Yanhong Yuan, Prithviraj Banerjee:
ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment. Great Lakes Symposium on VLSI 1999: 64-67 - [c138]Jim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran:
An Incremental Floorplanner. Great Lakes Symposium on VLSI 1999: 248-251 - [c137]Yanhong Yuan, Prithviraj Banerjee:
A Parallel 3-D Capacitance Extraction Program. HiPC 1999: 202-206 - [c136]