default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID10th HEART 2019: Nagasaki, Japan
- Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2019, Nagasaki, Japan, June 6-7, 2019. ACM 2019, ISBN 978-1-4503-7255-8
FPGA
- Anuj Vaishnav
, Khoa Dang Pham, Dirk Koch:
Heterogeneous Resource-Elastic Scheduling for CPU+FPGA Architectures. 1:1-1:6 - Fumiya Kono, Naohito Nakasato:
Performance Evaluation of Tsunami Simulation Exploiting Temporal Parallelism on FPGAs using OpenCL. 2:1-2:6 - Brett Grady, Jason Helge Anderson:
Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs. 3:1-3:6 - Kristiyan Manev, Anuj Vaishnav, Charalampos Kritikakis, Dirk Koch:
Scalable Filtering Modules for Database Acceleration on FPGAs. 4:1-4:6
System Software and Platform
- Luc Forget, Yohann Uguen, Florent de Dinechin, David Thomas:
A type-safe arbitrary precision arithmetic portability layer for HLS tools. 5:1-5:6 - Ryota Watanabe, Saika Ura, Qian Zhao, Takaichi Yoshida:
Implementation of FPGA Building Platform as a Cloud Service. 6:1-6:6 - Hideki Takase, Tomoya Mori, Kazuyoshi Takagi, Naofumi Takagi:
mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices. 7:1-7:6
High Performance Computing
- Kazuya Matsumoto, Naohito Nakasato, Toshiaki Hishinuma:
Effectiveness of performance tuning techniques for general matrix multiplication on the PEZY-SC2. 8:1-8:6 - Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano:
An ARM-based heterogeneous FPGA accelerator for Hall thruster simulation. 9:1-9:6 - Jens Huthmann, Shin Abiko, Artur Podobas, Kentaro Sano, Hiroyuki Takizawa:
Scaling Performance for N-Body Stream Computation with a Ring of FPGAs. 10:1-10:6
Architecture
- Takaaki Miyajima, Tomoya Hirao, Naoya Miyamoto, Jeongdo Son, Kentaro Sano:
A software bridged data transfer on a FPGA cluster by using pipelining and InfiniBand verbs. 11:1-11:6 - Ryusuke Egawa, Ryoma Saito, Masayuki Sato, Hiroaki Kobayashi:
A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism. 12:1-12:6 - Hossein Omidian, Guy G. F. Lemieux:
Software-based Dynamic Overlays Require Fast, Fine-grained Partial Reconfiguration. 13:1-13:6
Poster Session
- Hiromu Miyazaki, Junya Miura, Kenji Kise:
An Efficient Instruction Fetch Architecture for a RISC-V Soft Processor on an FPGA. 14:1-14:4 - Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano:
The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW. 15:1-15:4 - Iman Firmansyah, Changdao Du, Norihisa Fujita, Yoshiki Yamaguchi, Taisuke Boku:
FPGA-based Implementation of Memory-Intensive Application using OpenCL. 16:1-16:4 - Alexander Klemd, Marcel Eckert, Bernd Klauer, Jonas Hanselka, Delf Sachau:
A Parameterizable Feedback FxLMS Architecture for FPGA Platforms. 17:1-17:4 - Yuxi Sun, Akram Ben Ahmed, Hideharu Amano:
Acceleration of Deep Recurrent Neural Networks with an FPGA cluster. 18:1-18:4 - Changdao Du, Yoshiki Yamaguchi:
A High-Level Synthesis Design for a Scalable Hydrodynamic Simulation on OpenCL FPGA Platform. 19:1-19:4
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-14 22:23 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
