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ORCIDHideharu Amano
2020 – today
- 2025
[j125]Kaijie Wei
, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi, Takefumi Miyoshi:
Qu-Trefoil: Large-Scale Quantum Circuit Simulator Working on FPGA With SATA Storages. IEEE Trans. Computers 74(4): 1306-1321 (2025)- [j124]Atsutake Kosuge, Hirofumi Sumi, Naonobu Shimamoto, Yukinori Ochiai, Yurie Inoue, Hideharu Amano, Tohru Mogami, Yoshio Mita, Makoto Ikeda, Tadahiro Kuroda:
Agile-X: A Structured-ASIC Created With a Mask-Less Lithography System Enabling Low-Cost and Agile Chip Fabrication. IEEE Trans. Very Large Scale Integr. Syst. 33(3): 746-756 (2025) - [c392]Kaijie Wei, Devanshu Garg, Ryutaro Nagai, Takao Tomono, Hideharu Amano:
FPT-EMS: An FPGA Implementation Using NB-LDPC Code for Continuous-Variable Quantum Key Distribution. HEART 2025: 117-125 - [i3]Zirui Lin, Masayuki Takigahira, Naoya Terakado, Haris Gulzar, Monikka Roslianna Busto, Takeharu Eda, Katsutoshi Itoyama, Kazuhiro Nakadai, Hideharu Amano:
An Efficient GPU-based Implementation for Noise Robust Sound Source Localization. CoRR abs/2504.03373 (2025) - 2024
- [j123]Souhei Takagi, Takuya Kojima, Hideharu Amano, Morihiro Kuga, Masahiro Iida:
Applying Run-Length Compression to the Configuration Data of SLM Fine-Grained Reconfigurable Logic. IEICE Trans. Inf. Syst. 107(12): 1476-1483 (2024) - [j122]Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano:
Power Optimized Design Framework for FPGA Clusters. IPSJ Trans. Syst. LSI Des. Methodol. 17: 77-86 (2024) - [j121]Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano, Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho:
Optimized Two-Step Store Control for MTJ-Based Nonvolatile Flip-Flops to Minimize Store Energy Under Process and Temperature Variations. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 89-102 (2024) - [c391]Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida:
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. COOL CHIPS 2024: 1-6 - [c390]Zirui Lin, Katsutoshi Itoyama, Kazuhiro Nakadai, Hideharu Amano:
FPGA-based Low Power Acceleration of HARK Sound Source Localization. COOL CHIPS 2024: 1-6 - [c389]Kaijie Wei, Hideharu Amano, Ryohei Niwase, Yoshiki Yamaguchi:
A data compressor for FPGA-based state vector quantum simulators. HEART 2024: 63-70 - [c388]Hideharu Amano, Kensuke Iizuka:
Power analysis of an optical interconnected FPGA cluster for roadside units. ICCE 2024: 1-2 - [c387]Yuki Kameyama, Naoya Niwa, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
The Case for Coherence Directories in Memory Cubes. MCSoC 2024: 187-193 - 2023
- [j120]Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Designing low-diameter interconnection networks with multi-ported host-switch graphs. Concurr. Comput. Pract. Exp. 35(11) (2023) - [j119]Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi:
A Compression Router for Low-Latency Network-on-Chip. IEICE Trans. Inf. Syst. 106(2): 170-180 (2023) - [j118]Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano:
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability. IEICE Trans. Inf. Syst. 106(3): 337-348 (2023) - [j117]Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano:
Parallel Implementation of CNN on Multi-FPGA Cluster. IEICE Trans. Inf. Syst. 106(7): 1198-1208 (2023) - [j116]M. M. Imdad Ullah, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
A Multi-FPGA Implementation of FM-Index Based Genomic Pattern Search. IEICE Trans. Inf. Syst. 106(11): 1783-1795 (2023) - [j115]Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano:
Power Analysis and Power Modeling of Directly-Connected FPGA Clusters. IEICE Trans. Inf. Syst. 106(12): 1997-2005 (2023) - [j114]Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano:
A Scalable Body Bias Optimization Method Toward Low-Power CGRAs. IEEE Micro 43(1): 49-57 (2023) - [j113]Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho:
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 532-542 (2023) - [c386]Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano:
Parallel Implementation of Vision Transformer on a Multi-FPGA Cluster. candar 2023: 100-106 - [c385]Ziquan Qin, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai:
Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board. COOL CHIPS 2023: 1-6 - [c384]Kaijie Wei, Ryohei Niwase, Hideharu Amano, Yoshiki Yamaguchi, Takefumi Miyoshi:
A state vector quantum simulator working on FPGAs with extensible SATA storage. ICFPT 2023: 272-273 - [c383]Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano, Takefumi Miyoshi:
Enormous-Scale Quantum State Vector Calculation with FPGA-accelerated SATA storages. ICFPT 2023: 288-289 - [c382]Hideharu Amano:
Efficient FPGA Implementation of Amoeba-inspired SAT Solver with Feedback and Bounceback Control: Harnessing Variable-Level Parallelism for Large-Scale Problem Solving in Edge Computing. HEART 2023: 41-48 - [c381]Ryohei Niwase, Hikaru Harasawa, Yoshiki Yamaguchi, Kaijie Wei, Hideharu Amano:
A cost/power efficient storage system with directly connected FPGA and SATA disks. MCSoC 2023: 51-58 - [c380]Takumi Inage, Kensuke Iizuka, Hideharu Amano:
Board Allocation Algorithm for the Resource Management System of FiC. MCSoC 2023: 218-224 - [c379]Haris Gulzar, Muhammad Shakeel, Katsutoshi Itoyama, Kazuhiro Nakadai, Kenji Nishida, Hideharu Amano, Takeharu Eda:
FPGA based Power-Efficient Edge Server to Accelerate Speech Interface for Socially Assistive Robotics. SII 2023: 1-6 - 2022
- [j112]Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano:
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System. IEICE Trans. Inf. Syst. 105-D(12): 2008-2018 (2022) - [j111]Naoya Niwa, Hideharu Amano, Michihiro Koibuchi:
Boosting the Performance of Interconnection Networks by Selective Data Compression. IEICE Trans. Inf. Syst. 105-D(12): 2057-2065 (2022) - [j110]Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai:
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA. Int. J. Netw. Comput. 12(2): 425-445 (2022) - [j109]Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems 90: 104471 (2022) - [j108]Takuya Kojima, Ayaka Ohwada, Hideharu Amano:
Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning. IEEE Trans. Parallel Distributed Syst. 33(5): 1213-1230 (2022) - [c378]Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano:
Power Analysis of Directly-connected FPGA Clusters. COOL CHIPS 2022: 1-6 - [c377]Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano:
Body Bias Control on a CGRA based on Convex Optimization. COOL CHIPS 2022: 1-3 - [c376]Kohei Ito, Ryota Yasudo, Hideharu Amano:
Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches. FPL 2022: 143-147 - [c375]Morihiro Kuga, Masahiro Iida, Hideharu Amano:
FPL Demo: An FPGA-IP Prototype Chip for MEC devices. FPL 2022: 467 - [c374]Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano:
RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. HEART 2022: 1-9 - [c373]Yuchen Chen, Kaijie Wei, Hiroaki Nishi, Hideharu Amano:
An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board. CANDAR 2022: 83-89 - [c372]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR 2022: 117-123 - [c371]Aoi Hiruma, Kensuke Iizuka, Hideharu Amano:
Toward a training of CNNs on a multi-FPGA system. CANDARW 2022: 229-235 - [c370]Zhongyang Hou, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai:
An FPGA off-loading of HARK sound source localization. CANDARW 2022: 236-240 - [c369]Pengyu Huang, Kaijie Wei, Hideharu Amano, Kaori Ohkoda, Masashi Aono:
Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory. CANDARW 2022: 406-410 - [c368]Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems. MCSoC 2022: 45-52 - [c367]Zhou Yuqing, Naoya Niwa, Hideharu Amano:
Distance Aware Compression for Low Latency High Bandwidth Interconnection Network. MCSoC 2022: 361-367 - [c366]Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano:
Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations. NorCAS 2022: 1-7 - [c365]Yoshiya Shikama, Michihiro Koibuchi, Hideharu Amano:
A Hardware Trojan Exploiting Coherence Protocol on NoCs. PDCAT 2022: 301-313 - [c364]Ayaka Ohwada, Takuya Kojima, Hideharu Amano:
An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings. PDP 2022: 1-9 - [c363]Shigeyuki Takano, Hideharu Amano:
Reconfiguration Cost for Reconfigurable Computing Architectures. SNPD-Summer 2022: 62-67 - 2021
- [j107]Takeharu Ikezoe, Takuya Kojima, Hideharu Amano:
Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures. IEICE Trans. Electron. 104-C(6): 215-225 (2021) - [j106]Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano:
Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud). IEICE Trans. Inf. Syst. 104-D(8): 1321-1331 (2021) - [j105]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. IEICE Trans. Inf. Syst. 104-D(12): 2029-2039 (2021) - [j104]Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano:
CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis. IEICE Trans. Inf. Syst. 104-D(12): 2048-2056 (2021) - [j103]Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. IEICE Trans. Inf. Syst. 104-D(12): 2057-2067 (2021) - [j102]Miho Yamakura, Ryousei Takano, Akram Ben Ahmed, Midori Sugaya, Hideharu Amano:
A Multi-Tenant Resource Management System for Multi-FPGA Systems. IEICE Trans. Inf. Syst. 104-D(12): 2078-2088 (2021) - [j101]Kaijie Wei, Koki Honda, Hideharu Amano:
An implementation methodology for Neural Network on a Low-end FPGA Board. Int. J. Netw. Comput. 11(2): 172-197 (2021) - [j100]Ryota Yasudo, José Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo:
Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms. ACM Trans. Reconfigurable Technol. Syst. 14(3): 12:1-12:21 (2021) - [c362]Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
Implementing VTA, a tensor accelerator on Flow-in-Cloud. ACIT 2021: 46-50 - [c361]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT 2021: 51-55 - [c360]Hideto Kayashima, Hideharu Amano:
TCI Tester: Tester for Through Chip Interface. ASP-DAC 2021: 103-104 - [c359]Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano:
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System. COOL CHIPS 2021: 1-6 - [c358]Sannomiya Natsuho, Takeshi Ohkawa, Hideharu Amano, Midori Sugaya:
Power Consumption Reduction Method and Edge Offload Server for Multiple Robots. EDGE 2021: 1-19 - [c357]Ying Jie Yan, Hideharu Amano, Masashi Aono, Kaori Ohkoda, Shingo Fukuda, Kenta Saito, Seiya Kasai:
Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim. FPT 2021: 1-5 - [c356]Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano:
A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool. HEART 2021: 5:1-5:6 - [c355]Naoya Niwa, Hideharu Amano, Michihiro Koibuchi:
Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression. CANDAR 2021: 56-64 - [c354]Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano:
M-KUBOS/PYNQ Cluster for multi-access edge computing. CANDAR 2021: 95-101 - [c353]Hideto Kayashima, Hideharu Amano:
Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface. CANDAR (Workshops) 2021: 292-296 - [c352]Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai:
Weight Least Square Filter for Improving the Quality of Depth Map on FPGA. CANDAR (Workshops) 2021: 297-300 - [c351]Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano:
Parallel Implementation of CNN on Multi-FPGA Cluster. MCSoC 2021: 77-83 - [c350]Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho:
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops. MCSoC 2021: 273-280 - [c349]Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi:
A Case for Low-Latency Network-on-Chip using Compression Routers. PDP 2021: 134-142 - [c348]Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP 2021: 143-147 - 2020
- [j99]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. 103-D(1): 101-110 (2020) - [j98]Yuxi Sun, Hideharu Amano:
FiC-RNN: A Multi-FPGA Acceleration Framework for Deep Recurrent Neural Networks. IEICE Trans. Inf. Syst. 103-D(12): 2457-2462 (2020) - [j97]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. 103-D(12): 2471-2479 (2020) - [j96]Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano, Rodney Van Meter:
Extracting Success from IBM's 20-Qubit Machines Using Error-Aware Compilation. ACM J. Emerg. Technol. Comput. Syst. 16(3): 32:1-32:25 (2020) - [j95]Takuya Kojima, Nguyen Anh Vu Doan, Hideharu Amano:
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2383-2396 (2020) - [c347]M. M. Imdad Ullah, Akram Ben Ahmed, Hideharu Amano:
Implementation of FM-Index Based Pattern Search on a Multi-FPGA System. ARC 2020: 376-391 - [c346]Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda:
Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. COOL CHIPS 2020: 1-3 - [c345]Ryuta Kawano, Hiroki Matsutani, Hideharu Amano:
Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. CANDAR (Workshops) 2020: 93-99 - [c344]Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa:
FPGA Acceleration of ROS2-Based Reinforcement Learning Agents. CANDAR (Workshops) 2020: 106-112 - [c343]Manfred Orsztynowicz, Hideharu Amano, Kenichi Kubota, Takaaki Miyajima:
Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA. CANDAR 2020: 195-201 - [c342]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. CANDAR (Workshops) 2020: 211-217 - [c341]Kaijie Wei, Koki Honda, Hideharu Amano:
An implementation methodology for Neural Network on a Low-end FPGA Board. CANDAR 2020: 228-234 - [c340]Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system. CANDAR (Workshops) 2020: 277-281 - [c339]Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano:
CLAHE implementation on a low-end FPGA board by high-level synthesis. CANDAR (Workshops) 2020: 282-285 - [c338]Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa:
Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems. FPT 2020: 292-293 - [c337]Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano:
A Method of Partitioning Convolutional Layer to Multiple FPGAs. ISOCC 2020: 25-26 - [c336]Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. PDP 2020: 102-109
2010 – 2019
- 2019
- [j94]Takuya Kojima, Hideharu Amano:
A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures. IEICE Trans. Inf. Syst. 102-D(7): 1247-1256 (2019) - [j93]Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano:
Designing High-Performance Interconnection Networks with Host-Switch Graphs. IEEE Trans. Parallel Distributed Syst. 30(2): 315-330 (2019) - [c335]Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano:
Key-value Store Chip Design for Low Power Consumption. COOL CHIPS 2019: 1-3 - [c334]Yugo Yamauchi, Kazusa Musha, Hideharu Amano:
Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud. COOL CHIPS 2019: 1-3 - [c333]Michihiro Koibuchi, Lambert T. Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova:
Sparse 3-D NoCs with Inductive Coupling. DAC 2019: 49 - [c332]Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hideharu Amano:
Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA. FPL 2019: 411-412 - [c331]Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano:
Demonstration of Flow-in-Cloud: A Multi-FPGA System. FPL 2019: 417-418 - [c330]Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano:
An ARM-based heterogeneous FPGA accelerator for Hall thruster simulation. HEART 2019: 9:1-9:6 - [c329]Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano:
The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW. HEART 2019: 15:1-15:4 - [c328]Yuxi Sun, Akram Ben Ahmed, Hideharu Amano:
Acceleration of Deep Recurrent Neural Networks with an FPGA cluster. HEART 2019: 18:1-18:4 - [c327]Ryuta Kawano, Hiroki Matsutani, Hideharu Amano:
Deadlock-Free Layered Routing for Infiniband Networks. CANDAR Workshops 2019: 84-90 - [c326]Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano:
Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process. CANDAR Workshops 2019: 269-274 - [c325]Ryosuke Kazami, Hideharu Amano:
A Rapid Optimization Method for Visual Indirect SLAM Using a Subset of Feature Points. CANDAR Workshops 2019: 275-279 - [c324]Yasuaki Okamoto, Hideharu Amano:
Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel. CANDAR Workshops 2019: 280-284 - [c323]Takeharu Ikezoe, Takuya Kojima, Hideharu Amano:
A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-Volatile Configurable Memory. FPT 2019: 81-89 - [c322]Hayate Okuhara, Ryosuke Kazami, Hideharu Amano:
A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration. MCSoC 2019: 32-37 - [c321]Koki Honda, Kaijie Wei, Hideharu Amano:
FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board. MCSoC 2019: 53-60 - [c320]Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki:
A Preliminary Evaluation of Building Block Computing Systems. MCSoC 2019: 312-319 - [c319]Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano:
A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System. MCSoC 2019: 328-333 - [c318]Takuya Kojima, Hideharu Amano:
Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures. ReCoSoC 2019: 113-120 - [c317]Kazuei Hironaka, Akram Ben Ahmed, Hideharu Amano:
Multi-FPGA Management on Flow-in-Cloud Prototype System. SNPD 2019: 443-448 - [i2]Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano, Rodney Van Meter:
Extracting Success from IBM's 20-Qubit Machines Using Error-Aware Compilation. CoRR abs/1903.10963 (2019) - 2018
- [j92]Carlos Cesar Cortes Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano:
Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach. IEICE Trans. Inf. Syst. 101-D(4): 1116-1125 (2018) - [j91]Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano:
Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures. IEICE Trans. Inf. Syst. 101-D(6): 1532-1540 (2018) - [j90]Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. IEICE Trans. Inf. Syst. 101-D(9): 2258-2268 (2018) - [j89]Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano:
Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Int. J. Netw. Comput. 8(1): 124-139 (2018) - [j88]Hayate Okuhara, Akram Ben Ahmed, Hideharu Amano:
Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3241-3254 (2018) - [j87]Keita Azegami, Hayate Okuhara, Hideharu Amano:
Body Bias Control for Renewable Energy Source with a High Inner Resistance. IEEE Trans. Multi Scale Comput. Syst. 4(4): 605-612 (2018) - [j86]Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano:
Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1254-1267 (2018) - [c316]Kazusa Musha, Tomohiro Kudoh, Hideharu Amano:
Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud. ARC 2018: 43-54 - [c315]Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano:
Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study. ARC 2018: 142-150 - [c314]Ryosuke Kazami, Hayate Okuhara, Hideharu Amano:
Design automation methodology of a critical path monitor for adaptive voltage controls. COOL CHIPS 2018: 1-3 - [c313]Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Hiroyuki Noda, Hideharu Amano:
Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC. DDECS 2018: 55-60 - [c312]Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano:
Performance Prediction for Large-Scale Heterogeneous Platforms. FCCM 2018: 220 - [c311]Takuya Kojima, Hideharu Amano:
A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures. FPL 2018: 239-242 - [c310]Hideharu Amano:
Accelerator-in-Switch: A Novel Cooperation Framework for FPGAs and GPUs. FPT 2018: 22 - [c309]Ryota Yasudo, José Gabriel F. Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker:
Performance Estimation for Exascale Reconfigurable Dataflow Platforms. FPT 2018: 314-317 - [c308]Kaijie Wei, Koki Honda, Hideharu Amano:
FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks. FPT 2018: 425-428 - [c307]Takuya Kojima, Naoki Ando, Yusuke Matshushita, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano:
Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping. HEART 2018: 13:1-13:6 - [c306]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano:
k-Optimized Path Routing for High-Throughput Data Center Networks. CANDAR 2018: 99-105 - [c305]Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. CANDAR Workshops 2018: 182-185 - [c304]Hideki Shimura, Hiroyuki Noda, Hideharu Amano:
C4: An FPGA-based Compression Algorithm for ExpEther. CANDAR Workshops 2018: 356-362 - [c303]Tomohiro Totoki, Michihiro Koibuchi, Hideharu Amano:
An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking. CANDAR Workshops 2018: 363-369 - [c302]Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. MCSoC 2018: 146-153 - [c301]Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. NOCS 2018: 6:1-6:8 - [c300]Kimiyoshi Usami, Junya Akaike, Sosuke Akiba, Masaru Kudo, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami:
Energy Efficient Write Verify and Retry Scheme for MTJ Based Flip-Flop and Application. NVMSA 2018: 91-98 - [c299]Takeharu Ikezoe, Hideharu Amano, Junya Akaike, Kimiyoshi Usami, Masaru Kudo, Keizo Hiraga, Yusuke Shuto, Kojiro Yagami:
A Coarse Grained-Reconfigurable Accelerator with energy efficient MTJ-based Non-volatile Flip-flops. ReConFig 2018: 1-6 - [e4]Hideharu Amano:
Principles and Structures of FPGAs. Springer 2018, ISBN 978-981-13-0823-9 [contents] - 2017
- [j85]Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. IEICE Trans. Inf. Syst. 100-D(8): 1798-1806 (2017) - [j84]Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Layout-Oriented Routing Method for Low-Latency HPC Networks. IEICE Trans. Inf. Syst. 100-D(12): 2796-2807 (2017) - [j83]Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano:
Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. IEICE Trans. Inf. Syst. 100-D(12): 2828-2836 (2017) - [j82]Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura:
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers 66(4): 702-716 (2017) - [j81]Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang:
The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. 10(2): 15:1-15:17 (2017) - [j80]Hayate Okuhara, Yu Fujita, Kimiyoshi Usami, Hideharu Amano:
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1578-1582 (2017) - [c298]Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova:
A Case for Uni-directional Network Topologies in Large-Scale Clusters. CLUSTER 2017: 178-187 - [c297]Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash:
Panel discussions: "Cool chips for the next decade". COOL Chips 2017: 1-3 - [c296]Keita Azegami, Hayate Okuhara, Hideharu Amano:
Body bias control for renewable energy source with a high inner resistance. COOL Chips 2017: 1-3 - [c295]Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano:
Leveraging asymmetric body bias control for low power LSI design. COOL Chips 2017: 1-3 - [c294]Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano:
Body bias optimization for variable pipelined CGRA. FPL 2017: 1-4 - [c293]Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
In-switch approximate processing: Delayed tasks management for MapReduce applications. FPL 2017: 1-4 - [c292]Chiharu Tsuruta, Takahiro Kaneda, Naoki Nishikawa, Hideharu Amano:
Accelerator-in-switch: A framework for tightly coupled switching hub and an accelerator with FPGA. FPL 2017: 1-4 - [c291]Mankit Sit, Ryosuke Kazami, Hideharu Amano:
FPGA-based accelerator for losslessly quantized convolutional neural networks. FPT 2017: 295-298 - [c290]Takahiro Kaneda, Ryotaro Sakai, Naoki Nishikawa, Toshihiro Hanawa, Chiharu Tsuruta, Hideharu Amano:
Performance Evaluation of PEACH3: Field-Programmable Gate Array Switch for Tightly Coupled Accelerators. HEART 2017: 9:1-9:6 - [c289]Hiroyuki Noda, Ryotaro Sakai, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano:
Acceleration of the aggregation process in a Hall-thruster simulation using Intel FPGA SDK for OpenCL. HEART 2017: 20:1-20:6 - [c288]Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi:
High-Bandwidth Low-Latency Approximate Interconnection Networks. HPCA 2017: 469-480 - [c287]Akio Nomura, Junichiro Kadomoto, Tadahiro Kuroda, Hideharu Amano:
A Practical Collision Avoidance Method for an Inter-Chip Bus with Wireless Inductive through Chip Interface. CANDAR 2017: 126-131 - [c286]Yao Hu, Hiroaki Hara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
Towards Tightly-coupled Datacenter with Free-space Optical Links. ICCBDC 2017: 33-39 - [c285]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. ICPADS 2017: 664-673 - [c284]Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano:
Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. ICPP 2017: 322-331 - [c283]Yusuke Yoshida, Kimiyoshi Usami, Hideharu Amano:
Digital embedded memory scheme using voltage scaling and body bias separation for low-power system. ISOCC 2017: 148-149 - [c282]Junichiro Kadomoto, Hideharu Amano, Tadahiro Kuroda:
An inductive-coupling link for 3-D Network-on-Chips. ISOCC 2017: 150-151 - [c281]Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki:
Building block multi-chip systems using inductive coupling through chip interface. ISOCC 2017: 152-154 - [c280]Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano:
Scalable deep neural network accelerator cores with cubic integration using through chip interface. ISOCC 2017: 155-156 - [c279]Shinsuke Hamada, Atsushi Koshiba, Mitaro Namiki, Hideharu Amano:
Building block operating system for 3D stacked computer systems with inductive coupling interconnect. ISOCC 2017: 157-158 - [c278]Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. ISPAN-FCST-ISCC 2017: 52-59 - [c277]Ryuichi Sakamoto, Ryo Takata, Jun Ishii, Masaaki Kondo, Hiroshi Nakamura, Tetsui Ohkubo, Takuya Kojima, Hideharu Amano:
The Design and Implementation of Scalable Deep Neural Network Accelerator Cores. MCSoC 2017: 13-20 - [c276]Nguyen Anh Vu Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano:
Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA. MCSoC 2017: 143-150 - [c275]Hiroshi Nakahara, Ng. Anh Vu Doan, Ryota Yasudo, Hideharu Amano:
XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs. NOCS 2017: 17:1-17:8 - [c274]Naoki Nishikawa, Hideharu Amano, Keisuke Iwai:
Implementation of Bitsliced AES Encryption on CUDA-Enabled GPU. NSS 2017: 273-287 - [c273]Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano:
Glitch-aware variable pipeline optimization for CGRAs. ReConFig 2017: 1-6 - [c272]Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano:
Level-shifter-less approach for multi-VDD design to use body bias control in FD-SOI. VLSI-SoC 2017: 1-6 - [c271]Kimiyoshi Usami, Shunsuke Kogure, Yusuke Yoshida, Ryo Magasaki, Hideharu Amano:
Level-Shifter-Less Approach for Multi-VDD SoC Design to Employ Body Bias Control in FD-SOI. VLSI-SoC (Selected Papers) 2017: 1-21 - 2016
- [j79]Michihiro Koibuchi, Ikki Fujiwara, Kiyo Ishii, Shu Namiki, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh:
Optical network technologies for HPC: computer-architects point of view. IEICE Electron. Express 13(6): 20152007 (2016) - [j78]Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano:
Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. IEICE Trans. Electron. 99-C(8): 909-917 (2016) - [j77]Atsushi Koshiba, Mikiko Sato, Kimiyoshi Usami, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. IEICE Trans. Electron. 99-C(8): 926-935 (2016) - [j76]Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface. IEICE Trans. Inf. Syst. 99-D(12): 2871-2880 (2016) - [j75]Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 493-506 (2016) - [c270]Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. ICIS 2016: 1-6 - [c269]Naru Sugimoto, Takaaki Miyajima, Ryotaro Sakai, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Zynq Cluster for CFD Parametric Survey. ARC 2016: 287-299 - [c268]Junichiro Kadomoto, Tomoki Miyata, Hideharu Amano, Tadahiro Kuroda:
An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips. A-SSCC 2016: 41-44 - [c267]Satoshi Matsuoka, Hideharu Amano, Kengo Nakajima, Koji Inoue, Tomohiro Kudoh, Naoya Maruyama, Kenjiro Taura, Takeshi Iwashita, Takahiro Katagiri, Toshihiro Hanawa, Toshio Endo:
From FLOPS to BYTES: disruptive change in high-performance computing towards the post-moore era. Conf. Computing Frontiers 2016: 274-281 - [c266]Johannes Maximilian Kühn, Akram Ben Ahmed, Hayate Okuhara, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel:
MuCCRA4-BB: A fine-grained body biasing capable DRP. COOL Chips 2016: 1-3 - [c265]Johannes Maximilian Kühn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel:
Leveraging FDSOI through body bias domain partitioning and bias search. DAC 2016: 79:1-79:6 - [c264]Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano:
Body bias grain size exploration for a coarse grained reconfigurable accelerator. FPL 2016: 1-4 - [c263]Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano:
Variable pipeline structure for Coarse Grained Reconfigurable Array CMA. FPT 2016: 217-220 - [c262]Hiroshi Nakahara, Tetsui Ohkubo, Hideki Shimura, Ryotaro Sakai, Chiharu Tsuruta, Takahiro Kaneda, Hideharu Amano:
Trax solver on Zynq using incremental update algorithm. FPT 2016: 323-326 - [c261]Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. CANDAR 2016: 9-18 - [c260]Hideki Shimura, Takuji Mitsuishi, Masaki Kan, Takashi Yoshikawa, Hideharu Amano:
On-the-Fly Data Compression/Decompression Mechanism with ExpEther. CANDAR 2016: 112-118 - [c259]Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano:
Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. CANDAR 2016: 195-201 - [c258]Takuji Mitsuishi, Takahiro Kaneda, Sunao Torii, Hideharu Amano:
Implementing Breadth-First Search on a Compact Supercomputer Suiren. CANDAR 2016: 395-401 - [c257]Ryotaro Sakai, Naru Sugimoto, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano:
Acceleration of Full-PIC Simulation on a CPU-FPGA Tightly Coupled Environment. MCSoC 2016: 8-14 - [c256]Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. PDP 2016: 168-175 - 2015
- [j74]Koichiro Ishibashi, Nobuyuki Sugii, Shiro Kamohara, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham:
A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. IEICE Trans. Electron. 98-C(7): 536-543 (2015) - [j73]Atsushi Koshiba, Motoki Wada, Ryuichi Sakamoto, Mikiko Sato, Tsubasa Kosaka, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Hiroshi Nakamura, Mitaro Namiki:
A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. IEICE Trans. Electron. 98-C(7): 559-568 (2015) - [j72]Mai Izawa, Nobuaki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano:
A Co-Processor Design for an Energy Efficient Reconfigurable Accelerator CMA. Int. J. Netw. Comput. 5(1): 239-251 (2015) - [j71]Takaaki Miyajima, David B. Thomas, Hideharu Amano:
Courier: A Toolchain for Application Acceleration on Heterogeneous Platforms. IPSJ Trans. Syst. LSI Des. Methodol. 8: 105-115 (2015) - [j70]Takaaki Miyajima, David B. Thomas, Hideharu Amano:
A Toolchain for Dynamic Function Off-load on CPU-FPGA Platforms. J. Inf. Process. 23(2): 153-162 (2015) - [j69]Chiharu Tsuruta, Yohei Miki, Takuya Kuhara, Hideharu Amano, Masayuki Umemura:
Off-Loading LET Generation to PEACH2: A Switching Hub for High Performance GPU Clusters. SIGARCH Comput. Archit. News 43(4): 3-8 (2015) - [j68]Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano:
Breadth First Search on Cost-efficient Multi-GPU Systems. SIGARCH Comput. Archit. News 43(4): 58-63 (2015) - [c255]Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano, Hitoshi Murai, Masayuki Umemura, Mitsuhisa Sato:
Towards Unification of Accelerated Computing and Interconnection For Extreme-Scale Computing. ARC 2015: 463-474 - [c254]Seiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
A metamorphotic Network-on-Chip for various types of parallel applications. ASAP 2015: 98-105 - [c253]Johannes Maximilian Kühn, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel:
Fined-grained body biasing for frequency scaling in advanced SOI processes. COOL Chips 2015: 1-3 - [c252]Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano:
A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control. COOL Chips 2015: 1-3 - [c251]Johannes Maximilian Kühn, Dustin Peterson, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel:
Spatial and temporal granularity limits of body biasing in UTBB-FDSOI. DATE 2015: 876-879 - [c250]Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano:
Reduction calculator in an FPGA based switching Hub for high performance clusters. FPL 2015: 1-4 - [c249]Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang:
Significant papers from the first 25 years of the FPL conference. FPL 2015: 1-3 - [c248]Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano:
7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2. FPL 2015: 1 - [c247]Naru Sugimoto, Takuji Mitsuishi, Takahiro Kaneda, Chiharu Tsuruta, Ryotaro Sakai, Hideki Shimura, Hideharu Amano:
Trax solver on Zynq with Deep Q-Network. FPT 2015: 272-275 - [c246]Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano:
Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB. CANDAR 2015: 21-29 - [c245]Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano:
An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET. ISLPED 2015: 207-212 - [c244]Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. MCSoC 2015: 41-48 - [c243]Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano:
3D Shared Bus Architecture Using Inductive Coupling Interconnect. MCSoC 2015: 259-266 - [c242]Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura:
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. NOCS 2015: 16:1-16:8 - [c241]Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
Optimized Core-Links for Low-Latency NoCs. PDP 2015: 172-176 - [c240]Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano:
A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. ReConFig 2015: 1-6 - 2014
- [j67]Takayuki Akamine, Mohamad Sofian Abu Talip, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh. IEICE Trans. Inf. Syst. 97-D(5): 1225-1234 (2014) - [j66]Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. IPSJ Trans. Syst. LSI Des. Methodol. 7: 27-36 (2014) - [j65]Shimpei Nomura, Takuji Mitsuishi, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano:
Performance Analysis of the Multi-GPU System with ExpEther. SIGARCH Comput. Archit. News 42(4): 9-14 (2014) - [j64]Takuji Mitsuishi, Shimpei Nomura, Jun Suzuki, Yuki Hayashi, Masaki Kan, Hideharu Amano:
Accelerating Breadth First Search on GPU-BOX. SIGARCH Comput. Archit. News 42(4): 81-86 (2014) - [j63]Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
3D NoC with Inductive-Coupling Links for Building-Block SiPs. IEEE Trans. Computers 63(3): 748-763 (2014) - [c239]Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. ASP-DAC 2014: 843-848 - [c238]Koichiro Ishibashi, Nobuyuki Sugii, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham, Hideki Makiyama, Yoshiki Yamamoto, Hirofumi Shinohara, Toshiaki Iwamatsu, Yasuo Yamaguchi, Hidekazu Oda, Takumi Hasegawa, Shinobu Okanishi, Hiroshi Yanagita, Shiro Kamohara, Masaru Kadoshima, Keiichi Maekawa, Tomohiro Yamashita, Duc-Hung Le, Takumu Yomogita, Masaru Kudo, Kuniaki Kitamori, Shuya Kondo, Yuuki Manzawa:
A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. COOL Chips 2014: 1-3 - [c237]Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura:
A low power NoC router using the marching memory through type. COOL Chips 2014: 1-3 - [c236]Masaaki Kondo, Hiroaki Kobayashi, Ryuichi Sakamoto, Motoki Wada, Jun Tsukamoto, Mitaro Namiki, Weihan Wang, Hideharu Amano, Kensaku Matsunaga, Masaru Kudo, Kimiyoshi Usami, Toshiya Komoda, Hiroshi Nakamura:
Design and evaluation of fine-grained power-gating for embedded microprocessors. DATE 2014: 1-6 - [c235]Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano:
Low-latency wireless 3D NoCs via randomized shortcut chips. DATE 2014: 1-6 - [c234]Toru Katagiri, Hideharu Amano:
A high speed design and implementation of dynamically reconfigurable processor using 28NM SOI technology. FPL 2014: 1-4 - [c233]Honlian Su, Yu Fujita, Hideharu Amano:
Body bias control for a coarse grained reconfigurable accelerator implemented with Silicon on Thin BOX technology. FPL 2014: 1-6 - [c232]Yu Fujita, Koichiro Masuyama, Hideharu Amano:
Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery. FPT 2014: 354-357 - [c231]Naru Sugimoto, Hideharu Amano:
Hardware/software co-design architecture for Blokus Duo solver. FPT 2014: 358-361 - [c230]Shiro Kamohara, Nobuyuki Sugii, Koichiro Ishibashi, Kimiyoshi Usami, Hideharu Amano, Kazutoshi Kobayashi, Cong-Kha Pham:
A perpetuum mobile 32bit CPU on 65nm SOTB CMOS technology with reverse-body-bias assisted sleep mode. Hot Chips Symposium 2014: 1 - [c229]Takuya Kuhara, Takahiro Kaneda, Toshihiro Hanawa, Yuetsu Kodama, Taisuke Boku, Hideharu Amano:
A Preliminarily Evaluation of PEACH3: A Switching Hub for Tightly Coupled Accelerators. CANDAR 2014: 377-381 - [c228]Dipikarani Mishra, Mao Hatto, Takuya Kuhara, Naoyuki Fujita, Yasunori Osana, Hideharu Amano:
FPGA Implementation of Viscous Function in a Package for Computational Fluid Dynamics. CANDAR 2014: 608-610 - [c227]Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. ISSoC 2014: 1-7 - [c226]Yu Fujita, Kimiyoshi Usami, Hideharu Amano:
A Thermal Management System for Building Block Computing Systems. MCSoC 2014: 165-171 - [c225]Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura:
Design of a low power NoC router using Marching Memory Through type. NOCS 2014: 111-118 - [i1]Takaaki Miyajima, David B. Thomas, Hideharu Amano:
An Automatic Mixed Software Hardware Pipeline Builder for CPU-FPGA Platforms. CoRR abs/1408.4969 (2014) - 2013
- [j62]Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki:
Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Trans. Electron. 96-C(4): 404-412 (2013) - [j61]Amila Akagic, Hideharu Amano:
High-Speed Fully-Adaptable CRC Accelerators. IEICE Trans. Inf. Syst. 96-D(6): 1299-1308 (2013) - [j60]Hideharu Amano:
Foreword. IEICE Trans. Inf. Syst. 96-D(8): 1581 (2013) - [j59]Hideharu Amano:
Foreword. IEICE Trans. Inf. Syst. 96-D(12): 2513 (2013) - [j58]Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs. IEICE Trans. Inf. Syst. 96-D(12): 2753-2764 (2013) - [j57]Mohamad Sofian Abu Talip, Takayuki Akamine, Mao Hatto, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Adaptive Flux Calculation Scheme in Advection Term Computation Using Partial Reconfiguration. Int. J. Netw. Comput. 3(2): 289-306 (2013) - [j56]Amila Akagic, Hideharu Amano:
Design and Implementation of IP-based iSCSI Offload Engine on an FPGA. IPSJ Trans. Syst. LSI Des. Methodol. 6: 112-121 (2013) - [j55]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c224]Rie Uno, Nobuaki Ozaki, Hideharu Amano:
Research of PE Array Connection Network for Cool Mega-Array. AINA Workshops 2013: 144-149 - [c223]Jorge Hiraiwa, Hideharu Amano:
An FPGA Implementation of Reconfigurable Real-Time Vision Architecture. AINA Workshops 2013: 150-155 - [c222]Kugami Daiki, Takaaki Miyajima, Hideharu Amano:
A Circuit Division Method for High-Level Synthesis on Multi-FPGA Systems. AINA Workshops 2013: 156-161 - [c221]Takuya Kuhara, Takaaki Miyajima, Masato Yoshimi, Hideharu Amano:
An FPGA Acceleration for the Kd-tree Search in Photon Mapping. ARC 2013: 25-36 - [c220]Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A case for wireless 3D NoCs for CMPs. ASP-DAC 2013: 23-28 - [c219]Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links. COOL Chips 2013: 1-3 - [c218]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c217]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c216]David B. Thomas, Hideharu Amano:
A fully pipelined FPGA architecture for stochastic simulation of chemical systems. FPL 2013: 1-7 - [c215]Akihito Tsusaka, Mai Izawa, Rie Uno, Nobuyuki Ozaki, Hideharu Amano:
A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMA. FPL 2013: 1-4 - [c214]Rie Uno, Nobuaki Ozaki, Mai Izawa, Akihito Tsusaka, Takaaki Miyajima, Hideharu Amano:
A speculative gather system for Cool Mega-Array. FPT 2013: 346-349 - [c213]Mohamad Sofian Abu Talip, Takayuki Akamine, Mao Hatto, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Partially reconfigurable flux calculation scheme in advection term computation. FPT 2013: 382-385 - [c212]Hongliang Su, Weihan Wang, Kuniaki Kitamori, Hideharu Amano:
A low power reconfigurable accelerator using a back-gate bias control technique. FPT 2013: 390-393 - [c211]Takaaki Miyajima, Takuya Kuhara, Toshihiro Hanawa, Hideharu Amano, Taisuke Boku:
Task level pipelining with PEACH2: An FPGA switching fabric for high performance computing. FPT 2013: 466-469 - [c210]Naru Sugimoto, Takaaki Miyajima, Takuya Kuhara, Yuki Katuta, Takushi Mitsuichi, Hideharu Amano:
Artificial intelligence of Blokus Duo on FPGA using Cyber Work Bench. FPT 2013: 498-501 - [c209]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - [c208]Hideharu Amano:
Tutorial: Introduction to Interconnection Networks from System Area Network to Network on Chips. CANDAR 2013: 15-16 - [c207]Mai Izawa, Nobuyuki Ozaki, Yusuke Koizumi, Rie Uno, Hideharu Amano:
A Co-processor Design of an Energy Efficient Reconfigurable Accelerator CMA. CANDAR 2013: 148-154 - [c206]Daisuke Sasaki, Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity. ICA3PP (2) 2013: 77-85 - [c205]Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture. NOCS 2013: 1-8 - [c204]Remi Chaintreuil, Rie Uno, Hideharu Amano:
MCMA: A modular processing elements array based low-power coarse-grained reconfigurable accelerator. ReConFig 2013: 1-6 - 2012
- [j54]Hideharu Amano:
Foreword. IEICE Trans. Inf. Syst. 95-D(2): 293 (2012) - [j53]Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA. IEICE Trans. Inf. Syst. 95-D(10): 2369-2376 (2012) - [j52]Hideharu Amano:
Foreword. IEICE Trans. Inf. Syst. 95-D(12): 2749 (2012) - [c203]Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration. ARC 2012: 215-226 - [c202]Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Vertical Link On/Off Control Methods for Wireless 3-D NoCs. ARCS 2012: 212-224 - [c201]Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC 2012: 407-412 - [c200]Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano:
Trade-off analysis of fine-grained power gating methods for functional units in a CPU. COOL Chips 2012: 1-3 - [c199]Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics. FPL 2012: 136-142 - [c198]Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 - [c197]Amila Akagic, Hideharu Amano:
Performance analysis of fully-adaptable CRC accelerators on an FPGA. FPL 2012: 575-578 - [c196]Amila Akagic, Hideharu Amano:
A study of adaptable co-processors for Cyclic Redundancy Check on an FPGA. FPT 2012: 119-124 - [c195]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura:
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 - [c194]Takaaki Miyajima, David B. Thomas, Hideharu Amano:
A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU. ICNC 2012: 175-181 - [c193]Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova:
A case for random shortcut topologies for HPC interconnects. ISCA 2012: 177-188 - [c192]Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano:
Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. MCSoC 2012: 59-66 - [c191]Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki:
Removing Context Memory from a Multi-context Dynamically Reconfigurable Processor. MCSoC 2012: 92-99 - [c190]Hideharu Amano:
Castle of Chips: A New Chip Stacking Structure with Wireless Inductive Coupling for Large Scale 3-D Multicore Systems. NBiS 2012: 820-825 - [c189]Toru Katagiri, Kazuei Hironaka, Hideharu Amano:
Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array. NBiS 2012: 826-831 - [c188]Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Dynamically reconfigurable flux limiter functions in MUSCL scheme. ReCoSoC 2012: 1-7 - [c187]Ryuichi Sakamoto, Mikiko Sato, Yusuke Koizumi, Hideharu Amano, Mitaro Namiki:
An OpenCL Runtime Library for Embedded Multi-Core Accelerator. RTCSA 2012: 419-422 - [r1]Hiroshi Sasaki, Hideharu Amano, Kimiyoshi Usami, Masaaki Kondo, Mitaro Namiki, Hiroshi Nakamura:
Geyser. Handbook of Energy-Aware and Green Computing 2012: 49-65 - 2011
- [j51]Lei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano:
A Leakage Efficient Data TLB Design for Embedded Processors. IEICE Trans. Inf. Syst. 94-D(1): 51-59 (2011) - [j50]Zhao Lei, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano:
A Leakage Efficient Instruction TLB Design for Embedded Processors. IEICE Trans. Inf. Syst. 94-D(8): 1565-1574 (2011) - [j49]Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano:
Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2619-2627 (2011) - [j48]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. Inf. Media Technol. 6(4): 1092-1102 (2011) - [j47]Zhao Lei, Daisuke Ikebuchi, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura, Hideharu Amano:
Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. IPSJ Trans. Syst. LSI Des. Methodol. 4: 182-192 (2011) - [j46]Arda Karaduman, Iver Stubdal, Hideharu Amano:
Design and Implementation of Echo Instructions for an Embedded Processor. IPSJ Trans. Syst. LSI Des. Methodol. 4: 222-231 (2011) - [j45]Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano:
An analytical network performance model for SIMD processor CSX600 interconnects. J. Syst. Archit. 57(1): 146-159 (2011) - [j44]Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31(6): 6-18 (2011) - [j43]Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
An implementation of out-of-order execution system for acceleration of computational fluid dynamics on FPGAs. SIGARCH Comput. Archit. News 39(4): 50-55 (2011) - [j42]Amila Akagic, Hideharu Amano:
High speed CRC with 64-bit generator polynomial on an FPGA. SIGARCH Comput. Archit. News 39(4): 72-77 (2011) - [j41]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga:
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers 60(6): 783-799 (2011) - [j40]Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 520-533 (2011) - [j39]Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano:
A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet. IEEE Trans. Parallel Distributed Syst. 22(2): 217-230 (2011) - [c186]Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami:
Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction. ARC 2011: 230-241 - [c185]Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo:
Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88 - [c184]Nobuaki Ozaki, Kimiyoshi Usami, Hideharu Amano, Mitaro Namiki, Hiroshi Nakamura, Masaaki Kondo:
SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. COOL Chips 2011: 1-3 - [c183]Kazuei Hironaka, Nobuaki Ozaki, Hideharu Amano:
The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator. FPT 2011: 1-4 - [c182]Masayuki Kimura, Kazuei Hironaka, Hideharu Amano:
Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. FPT 2011: 1-8 - [c181]Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo:
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT 2011: 1-8 - [c180]Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano:
Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects. ICNC 2011: 50-57 - [c179]Akihiro Shitara, Tetsuya Nakahama, Masahiro Yamada, Toshiaki Kamata, Yuri Nishikawa, Masato Yoshimi, Hideharu Amano:
Vegeta: An Implementation and Evaluation of Development-Support Middleware on Multiple OpenCL Platform. ICNC 2011: 141-147 - [c178]Tetsuya Nakahama, Masahiro Yamada, Masato Yoshimi, Hideharu Amano:
Proposal of Auto MPI Expansion Tool for Cell Broadband Engine Cluster. ICNC 2011: 166-172 - [c177]Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura:
On-chip detection methodology for break-even time of power gated function units. ISLPED 2011: 241-246 - [c176]Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A vertical bubble flow network using inductive-coupling for 3-D CMPs. NOCS 2011: 49-56 - [c175]Kazuei Hironaka, Hideharu Amano:
Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth. ReConFig 2011: 404-409 - [c174]Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano:
A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) 2011: 106-108 - [p2]Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano:
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. Low Power Networks-on-Chip 2011: 21-43 - [p1]Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
3-D NoC on Inductive Wireless Interconnect. 3D Integration for NoC-based SoC Architectures 2011: 225-248 - 2010
- [j38]Hideki Yamada, Yui Ogawa, Tomonori Ooya, Tomoya Ishimori, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri:
Automatic Pipeline Construction Focused on Similarity of Rate Law Functions for an FPGA-based Biochemical Simulator. IPSJ Trans. Syst. LSI Des. Methodol. 3: 244-256 (2010) - [j37]Hirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system. SIGARCH Comput. Archit. News 38(4): 8-13 (2010) - [c173]Masato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer:
A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster. ARC 2010: 372-381 - [c172]Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo:
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC 2010: 369-370 - [c171]Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano:
MuCCRA-3: a low power dynamically reconfigurable processor array. ASP-DAC 2010: 377-378 - [c170]Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano:
Wire congestion aware synthesis for a dynamically reconfigurable processor. FPT 2010: 300-303 - [c169]Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano:
Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. FPT 2010: 349-352 - [c168]Yui Ogawa, Tomonori Ooya, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri:
A datapath classification method for FPGA-based scientific application accelerator systems. FPT 2010: 441-444 - [c167]Zhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki:
Reducing instruction TLB's leakage power consumption for embedded processors. Green Computing Conference 2010: 477-484 - [c166]Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
Adaptive power gating for function units in a microprocessor. ISQED 2010: 29-37 - [c165]Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A variable-pipeline on-chip router optimized to traffic pattern. NoCArc@MICRO 2010: 57-62 - [c164]José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. NAS 2010: 218-227 - [c163]Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. NAS 2010: 431-438 - [c162]Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS 2010: 61-68 - [e3]Phaophak Sirisuk, Fearghal Morgan, Tarek A. El-Ghazawi, Hideharu Amano:
Reconfigurable Computing: Architectures, Tools and Applications, 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010. Proceedings. Lecture Notes in Computer Science 5992, Springer 2010, ISBN 978-3-642-12132-6 [contents]
2000 – 2009
- 2009
- [j36]Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Trans. Inf. Syst. 92-D(4): 575-583 (2009) - [j35]Iver Stubdal, Arda Karaduman, Hideharu Amano:
Code Compression with Split Echo Instructions. IEICE Trans. Inf. Syst. 92-D(9): 1650-1656 (2009) - [j34]Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano:
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distributed Syst. 20(8): 1126-1141 (2009) - [j33]Hideharu Amano, Tadao Nakamura:
Guest Editors' Introduction: ICFPT 2007. ACM Trans. Reconfigurable Technol. Syst. 2(2): 7:1-7:2 (2009) - [c161]Tomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri:
Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator. ARC 2009: 368-373 - [c160]Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano:
Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS 2009: 171-182 - [c159]Hideharu Amano:
Japanese Dynamically Reconfigurable Processors. ERSA 2009: 19-28 - [c158]Toru Sano, Yoshiki Saito, Hideharu Amano:
Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. ERSA 2009: 112-118 - [c157]Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano:
A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. ERSA 2009: 283-286 - [c156]Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano:
MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL 2009: 6-11 - [c155]Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano:
Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. FPL 2009: 530-533 - [c154]Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs. FPL 2009: 654-657 - [c153]Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano:
Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator. FPL 2009: 679-682 - [c152]Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano:
Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. FPT 2009: 104-111 - [c151]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga:
Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378 - [c150]José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Balanced Dimension-Order Routing for k-ary n-cubes. ICPP Workshops 2009: 499-506 - [c149]Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano:
An on/off link activation method for low-power ethernet in PC clusters. IPDPS 2009: 1-11 - [c148]Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano:
Evaluation of a multicore reconfigurable architecture with variable core sizes. IPDPS 2009: 1-8 - [c147]Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano:
Performance Analysis of ClearSpeed's CSX600 Interconnects. ISPA 2009: 203-210 - [c146]José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano:
An On/Off Link Activation Method for Power Regulation in InfiniBand. PDPTA 2009: 289-295 - [c145]Hideki Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri:
A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA. ReConFig 2009: 125-130 - [c144]Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura:
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386 - 2008
- [j32]Vu Manh Tuan, Hideharu Amano:
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors. IEICE Trans. Inf. Syst. 91-D(9): 2312-2322 (2008) - [j31]Vasutan Tunbunheng, Hideharu Amano:
A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays. IEICE Trans. Inf. Syst. 91-D(11): 2655-2665 (2008) - [j30]Vu Manh Tuan, Hideharu Amano:
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors. IEICE Trans. Inf. Syst. 91-D(12): 2793-2803 (2008) - [c143]Vu Manh Tuan, Hideharu Amano:
A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor. ARC 2008: 171-182 - [c142]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang:
Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC 2008: 55-60 - [c141]Vu Manh Tuan, Hideharu Amano:
A Method for Capturing State Data on Dynamically Reconfigurable Processors. ERSA 2008: 208-214 - [c140]Masaru Kato, Yohei Hasegawa, Hideharu Amano:
Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs. ERSA 2008: 215-221 - [c139]Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano:
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. FPL 2008: 215-220 - [c138]Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL 2008: 269-274 - [c137]Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano:
Power reduction techniques for Dynamically Reconfigurable Processor Arrays. FPL 2008: 305-310 - [c136]Masato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano:
Practical implementation of a network-based stochastic biochemical simulation system on an FPGA. FPL 2008: 663-666 - [c135]Takuro Nakamura, Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano:
Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors. FPT 2008: 137-144 - [c134]Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs. FPT 2008: 193-200 - [c133]Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano:
Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT 2008: 329-332 - [c132]Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura:
A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617 - [c131]Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano:
Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN 2008: 281-288 - [c130]Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston:
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS 2008: 13-22 - [c129]Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano:
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS 2008: 23-32 - [c128]Yuken Kishimoto, Shinichiro Haruyama, Hideharu Amano:
Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor. ReConFig 2008: 247-252 - 2007
- [j29]Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano:
Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices. IEICE Trans. Inf. Syst. 90-D(2): 473-481 (2007) - [j28]Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Trans. Inf. Syst. 90-D(12): 1914-1922 (2007) - [j27]Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano:
An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks. IEEE Trans. Parallel Distributed Syst. 18(3): 320-333 (2007) - [j26]Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano:
Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs. IEEE Trans. Parallel Distributed Syst. 18(9): 1282-1295 (2007) - [c127]Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka:
Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA. CIT 2007: 567-572 - [c126]Vu Manh Tuan, Yohei Hasegawa, Hideharu Amano:
Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor. ERSA 2007: 203-206 - [c125]Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano:
FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method. FPL 2007: 254-259 - [c124]Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL 2007: 383-388 - [c123]Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka:
A High Speed License Plate Recognition System on an FPGA. FPL 2007: 554-557 - [c122]Yohei Hasegawa, Hideharu Amano:
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. FPL 2007: 796-799 - [c121]Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri:
A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator. FPL 2007: 808-811 - [c120]Masato Yoshimi, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Hideki Yamada, Hiroaki Kitano, Hideharu Amano:
A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGA. FPT 2007: 193-200 - [c119]Satoshi Tsutsumi, Vasutan Tunbunheng, Yohei Hasegawa, Adepu Parimala, Takuro Nakamura, Takashi Nishimura, Hideharu Amano:
Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays. FPT 2007: 273-276 - [c118]Vu Manh Tuan, Hideharu Amano:
A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors. FPT 2007: 357-360 - [c117]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP 2007: 75 - [c116]Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano:
Performance Improvement Methodology for ClearSpeed's CSX600. ICPP 2007: 77 - [c115]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS 2007: 1-10 - [c114]Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano:
Performance evaluation on low-latency communication mechanism of DIMMnet-2. Parallel and Distributed Computing and Networks 2007: 57-62 - [c113]Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo:
Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. PDPTA 2007: 787-793 - [e2]Hideharu Amano, Andy Ye, Takeshi Ikenaga:
2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007. IEEE 2007, ISBN 1-4244-1472-5 [contents] - 2006
- [j25]Hideharu Amano:
A Survey on Dynamically Reconfigurable Processors. IEICE Trans. Commun. 89-B(12): 3179-3187 (2006) - [j24]Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano:
A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. IEEE Trans. Parallel Distributed Syst. 17(12): 1425-1437 (2006) - [c112]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. PDCS 2006: 24-31 - [c111]Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano:
Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor. ARC 2006: 115-121 - [c110]Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano:
A Parametric Study of Scalable Interconnects on FPGAs. ERSA 2006: 130-135 - [c109]Hideharu Amano, Yohei Hasegawa, Shohei Abe, Kenichiro Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura:
A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. FPL 2006: 1-6 - [c108]Yasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano:
Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip. FPL 2006: 1-6 - [c107]Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano:
An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems. FPL 2006: 1-6 - [c106]Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano:
An adaptive Viterbi decoder on the dynamically reconfigurable processor. FPT 2006: 285-288 - [c105]Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano:
Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. ICPP 2006: 479-486 - [c104]Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, Hideharu Amano:
Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. IPDPS 2006 - [c103]Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano:
A cost-effective context memory structure for dynamically reconfigurable processors. IPDPS 2006 - [c102]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA 2006: 207-218 - 2005
- [j23]Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing. IEICE Trans. Inf. Syst. 88-D(1): 109-118 (2005) - [j22]Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
Path selection algorithm: the strategy for designing deterministic routing from alternative paths. Parallel Comput. 31(1): 117-130 (2005) - [j21]Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano:
The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). Parallel Comput. 31(3-4): 352-370 (2005) - [j20]Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano:
Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster. IEEE Trans. Parallel Distributed Syst. 16(8): 747-759 (2005) - [c101]Katsuaki Deguchi, Shohei Abe, Masayasu Suzuki, Kenichiro Anjo, Toru Awashima, Hideharu Amano:
Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor. ARCS Workshops 2005: 12-18 - [c100]Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki:
Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor. FCCM 2005: 315-316 - [c99]Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano:
Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. FPGA 2005: 265 - [c98]Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa:
An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration? FPL 2005: 347-352 - [c97]Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano:
A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA. FPL 2005: 574-577 - [c96]Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri:
Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA. FPL 2005: 666-669 - [c95]Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano:
RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices. FPT 2005: 129-136 - [c94]Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima:
An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. FPT 2005: 163-170 - [c93]Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano:
The Design of Scalable Stochastic Biochemical Simulator on FPGA. FPT 2005: 339-340 - [c92]Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus. ICPP 2005: 567-576 - [c91]Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano:
Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops 2005: 273-280 - [c90]Yasunori Osana, Tomonori Fukushima, Masato Yoshimi, Yow Iwaoka, Yuichiro Shibata, Hiroaki Kitano, Akira Funahashi, Noriko Hiroi, Hideharu Amano:
An FPGA-Based, Multi-model Simulation Method for Biochemical Systems. IPDPS 2005 - [c89]Shunsuke Kurotaki, Noriaki Suzuki, Kazuhiro Nakadai, Hiroshi G. Okuno, Hideharu Amano:
Implementation of active direction-pass filter on dynamically reconfigurable processor. IROS 2005: 3175-3180 - [c88]Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano:
Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. ISHPC 2005: 211-218 - [c87]Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo:
Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. PDCAT 2005: 778-780 - [c86]Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano:
Implementation of ISIS-SimpleScalar. PDPTA 2005: 117-123 - [c85]Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo:
A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. PDPTA 2005: 461-467 - [c84]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA 2005: 1343-1349 - 2004
- [j19]Yasunori Osana, Tomonori Fukushima, Masato Yoshimi, Hideharu Amano:
An FPGA-Based Acceleration Method for Metabolic Simulation. IEICE Trans. Inf. Syst. 87-D(8): 2029-2037 (2004) - [c83]Masato Sumiyoshi, Takashi Midorikawa, Yasuki Tanabe, Hideharu Amano:
Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory. PDCS 2004: 296-301 - [c82]Yasunori Osana, Tomonori Fukushima, Hideharu Amano:
ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA. ASP-DAC 2004: 731-733 - [c81]Masahiko Kawamura, Hideharu Amano:
Future reconfigurable computing system. ASP-DAC 2004: 798 - [c80]Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura:
Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. EUC 2004: 301-311 - [c79]Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima:
Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. FCCM 2004: 328-329 - [c78]Masato Yoshimi, Yasunori Osana, Tomonori Fukushima, Hideharu Amano:
Stochastic Simulation for Biochemical Reactions on FPGA. FPL 2004: 105-114 - [c77]Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki:
Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. FPL 2004: 464-473 - [c76]Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima:
Stream applications on the dynamically reconfigurable processor. FPT 2004: 137-144 - [c75]Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. IPDPS 2004 - [c74]Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano:
A New Memory Module for Memory Intensive Applications. PARELEC 2004: 123-128 - 2003
- [c73]Tomohiro Otsuka, Konosuke Watanabe, Junichiro Tsuchiya, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Hideharu Amano:
Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System. Applied Informatics 2003: 738-743 - [c72]Kenta Yasufuku, Riku Ogawa, Keisuke Iwai, Hideharu Amano:
MAPLE chip: a processing element for a static scheduling centric multiprocessor. ASP-DAC 2003: 575-576 - [c71]Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hideharu Amano, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh:
Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems. CCGRID 2003: 318-325 - [c70]Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano:
Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster. CLUSTER 2003: 395- - [c69]Hideharu Amano, Akiya Jouraku, Kenichiro Anjo:
A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device. FPL 2003: 161-170 - [c68]Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo:
Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. FPL 2003: 171-180 - [c67]Yasunori Osana, Tomonori Fukushima, Hideharu Amano:
Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform. FPL 2003: 766-775 - [c66]Yoshinori Adachi, Kenichiro Ishikawa, Satoshi Tsutsumi, Hideharu Amano:
An implementation of the Rijndael on Async-WASMII. FPT 2003: 44-51 - [c65]Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano:
Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies. ICPP 2003: 527- - [c64]Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano:
Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. PDPTA 2003: 1148-1154 - [c63]Noriaki Suzuki, Hideharu Amano:
Performance Evaluation of Instruction Set Architecture of MBP-Light: A Distributed Memory Controller for a Large Scale Multiprocessor. PDPTA 2003: 1155-1164 - [e1]Alexander V. Veidenbaum, Kazuki Joe, Hideharu Amano, Hideo Aiso:
High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings. Lecture Notes in Computer Science 2858, Springer 2003, ISBN 3-540-20359-1 [contents] - 2002
- [j18]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Clust. Comput. 5(1): 7-17 (2002) - [c62]Naoto Kaneko, Hideharu Amano:
A General Hardware Design Model for Multicontext FPGAs. FPL 2002: 1037-1047 - [c61]Naoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu Amano:
RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing. FPL 2002: 1118-1121 - [c60]Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano, Akira Funahashi:
Routing Algorithms Based on 2D Turn Model for Irregular Networks. ISPAN 2002: 289-294 - [c59]Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano:
Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. PARELEC 2002: 9-14 - [c58]Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing. PDPTA 2002: 1431-1437 - 2001
- [j17]Hiroaki Nishi, Koji Tasho, Tomohiro Kudoh, Hideharu Amano:
A network switch for supporting high-performance parallel processing by computers distributed in local areas. Syst. Comput. Jpn. 32(14): 24-33 (2001) - [j16]Yulu Yang, Akira Funahashi, Akiya Jouraku, Hiroaki Nishi, Hideharu Amano, Toshinori Sueyoshi:
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. IEEE Trans. Parallel Distributed Syst. 12(7): 701-715 (2001) - [c57]Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano:
MMLRU Selection Function: An Output Selection Function on Adaptive Routing. PDCS 2001: 1-6 - [c56]Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano:
A prototype chip of multicontext FPGA with DRAM for virtual hardware. ASP-DAC 2001: 17-18 - [c55]Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano:
The impact of output selection function on adaptive routing. CATA 2001: 241-246 - [c54]Shinji Nishimura, Tomohiro Kudoh, Hiroaki Nishi, Junji Yamamoto, Ryuichiro Ueno, Katsuyoshi Harasawa, Shuji Fukuda, Yasutaka Shikichi, Shigeto Akutsu, Koji Tasho, Hideharu Amano:
RHiNET-3/SW: an 80-Gbit/s high-speed network switch for distributed parallel computing. Hot Interconnects 2001: 119-123 - [c53]Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano:
L-Turn Routing: An Adaptive Routing in Irregular Networks. ICPP 2001: 383-392 - 2000
- [j15]Shinji Nishimura, Katsuyoshi Harasawa, N. Matsudaira, Shigeto Akutsu, Tomohiro Kudoh, Hiroaki Nishi, Hideharu Amano:
RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection. New Gener. Comput. 18(2): 187-197 (2000) - [c52]Takahiro Kawaguchi, Takayuki Suzuki, Hideharu Amano:
A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system. ASP-DAC 2000: 31-32 - [c51]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
MEMOnet : Network interface plugged into a memory slot. CLUSTER 2000: 17-16 - [c50]Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano:
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. FCCM 2000: 291-294 - [c49]Yuichiro Shibata, Masaki Uno, Hideharu Amano, Koichiro Furuta, Taro Fujii, Masato Motomura:
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. FCCM 2000: 295-296 - [c48]Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano:
A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. FPL 2000: 475-484 - [c47]Hideharu Amano, Yuichiro Shibata, Masaki Uno:
Reconfigurable Systems: New Activities in Asia. FPL 2000: 585-594 - [c46]Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano:
Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware. FPL 2000: 685-694 - [c45]Hiroaki Nishi, Koji Tasho, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano:
A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing. HPDC 2000: 296-297 - [c44]Masaki Wakabayashi, Hideharu Amano:
Environment for Multiprocessor Simulator Development. ISPAN 2000: 64-71 - [c43]Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano:
On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN 2000: 186-194 - [c42]Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano:
Coherence Protocol for Home Proxy Cache on RHiNET. PDPTA 2000
1990 – 1999
- 1999
- [j14]Junji Yamamoto, Takashi Fujiwara, T. Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano:
Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. Parallel Comput. 25(9): 1081-1103 (1999) - [c41]Masaki Wakabayashi, Keisuke Inoue, Hideharu Amano:
ISIS: Multiprocessor Simulator Library. Applied Informatics 1999: 198-200 - [c40]Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano:
A Routing Algorithm for DS-WDM Ring. Applied Informatics 1999: 562-565 - [c39]Takahiro Kawaguchi, Takashi Fujiwara, Katsuto Sakamoto, Keisuke Iwai, Hideharu Amano:
Floating Point Arithmetic Unit for the Custom Processor Maple. Applied Informatics 1999: 578-580 - [c38]Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hidenori Miyazaki, Koichi Higure, Xiao-ping Ling, Hideharu Amano:
Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System. ICPP Workshops 1999: 346-351 - [c37]Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano:
Internal Parallelization of Data-Driven Virtual Hardware. ICPP Workshops 1999: 366-373 - [c36]Qin Fan, Yulu Yang, Akira Funahashi, Hideharu Amano:
A Torus Assignment for an Interconnection Network Recursive Diagonal Torus. ISPAN 1999: 74-79 - [c35]Fumiharu Morisawa, Daisuke Kawakami, Kensuke Tanaka, Hideharu Amano:
An Educational System of LSI Design with Free-Wares for VDEC. MSE 1999: 61-62 - 1998
- [j13]Asami Miyajima, Kazumasa Nukata, Hideharu Amano, Yuichiro Anzai:
Design and implementation of reconfigurable sensing system for networked robots. Adv. Robotics 13(3): 253-254 (1998) - [j12]Ou Yamamoto, Takuya Terasawa, Hideharu Amano:
An analysis of fairness and overhead in the arbitration protocol of the IEEE Futurebus standard. Syst. Comput. Jpn. 29(13): 66-77 (1998) - [c34]Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano:
The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. ASP-DAC 1998: 337-338 - [c33]Hideharu Amano, Yuichiro Shibata:
Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial). ASP-DAC 1998: 453-457 - [c32]Yuichiro Shibata, Hidenori Miyazaki, Xiao-ping Ling, Hideharu Amano:
HOSMII: A Virtual Hardware Integrated with DRAM. IPPS/SPDP Workshops 1998: 85-90 - 1997
- [j11]Takuya Terasawa, Keisuke Inoue, Hitoshi Kurosawa, Hideharu Amano:
A study on snoop cache systems for single-chip multiprocessors. Syst. Comput. Jpn. 28(2): 62-72 (1997) - [c31]Takayuki Kamei, Masashi Sasahara, Hideharu Amano:
An LSI implementation of the simple serial synchronized multistage interconnection network. ASP-DAC 1997: 673-674 - [c30]Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Kenichiro Anjo, Tomohiro Kudoh:
The RDT network router chip. ASP-DAC 1997: 675-676 - [c29]Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, Keisuke Inoue, Hideharu Amano:
Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors. Euro-Par 1997: 793-797 - [c28]Kazumasa Nukata, Yuichiro Shibata, Hideharu Amano, Yuichiro Anzai:
A reconfigurable sensor-data processing system for personal robots. FPL 1997: 491-500 - [c27]Akira Funahashi, Toshihiro Hanawa, Hideharu Amano, Tomohiro Kudoh:
Adaptive Routing on the Recursive Diagonal Torus. ISHPC 1997: 171-182 - [c26]Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano:
Wavelength Division Multiple Access Ring - Virtual Topology on a Simple Ring Network. ISPAN 1997: 30-36 - [c25]Xiao-ping Ling, Yuichiro Shibata, Hidenori Miyazaki, Hideharu Amano, Koichi Higure:
Total System Image of the Reconfigurable Machine WASMII. PDPTA 1997: 1092-1096 - 1996
- [j10]Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi:
Recursive Diagonal Torus (RDT): An Interconnection Network for the Massively Parallel Computers. Syst. Comput. Jpn. 27(9): 43-54 (1996) - [c24]Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano:
An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware. FPL 1996: 55-64 - [c23]Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano:
ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. FPL 1996: 200-209 - [c22]Toshihiro Hanawa, Takashi Fujiwara, Hideharu Amano:
Hot spot contention and message combining in the simple serial synchronized multistage interconnection network. SPDP 1996: 298-305 - 1995
- [j9]Kyotaro Suzuki, Hideharu Amano, Yoshiyasu Takefuji:
Neural network parallel computing for multi-layer channel routing problems. Neurocomputing 8(2): 141-156 (1995) - [j8]Takuya Terasawa, Ou Yamamoto, Tomohiro Kudoh, Hideharu Amano:
A Performance Evaluation of the Multiprocessor Testbed ATTEMPT-0. Parallel Comput. 21(5): 701-730 (1995) - [j7]Kalidou Gaye, Toshihiro Hanawa, Hideharu Amano:
An analysis of the hot spot contention and message combining on the simple serial synchronized-multistage interconnection network. Syst. Comput. Jpn. 26(9): 1-12 (1995) - [j6]Xiao-ping Ling, Hideharu Amano:
WASMII: An MPLD with data-driven control on a virtual hardware. J. Supercomput. 9(3): 253-276 (1995) - [c21]Tomohiro Kudoh, Hideharu Amano, Takashi Matsumoto, Kei Hiraki, Yulu Yang, Katsunobu Nishimura, Koichi Yoshimura, Yasuhito Fukushima:
Hierarchical Bit-Map Directory Schemes on the RDT Interconnection Network for a Massively Parallel Processor JUMP-1. ICPP (1) 1995: 186-193 - [c20]Junji Yamamoto, D. Hattori, Jun-ichi Yamato, T. Tokuyoshi, Y. Yamaguchi, Hideharu Amano:
A Preprocessing System of the EULASH: An Environment for Efficient use of Multiprocessors with Local Memory. Parallel and Distributed Computing and Systems 1995: 68-71 - 1994
- [c19]Xiao-yu Chen, Xiao-ping Ling, Hideharu Amano:
Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware. FPL 1994: 208-219 - [c18]Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa:
Multistage Interconnection Networks with Multiple Outlets. ICPP (1) 1994: 1-8 - [c17]Masashi Sasahara, Jun Terada, Luo Zhou, Kalidou Gaye, Jun-ichi Yamato, Satoshi Ogura, Hideharu Amano:
SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture. ICPP (1) 1994: 117-120 - [c16]Yulu Yang, Hideharu Amano:
Message transfer algorithms on the recursive diagonal torus. ISPAN 1994: 310-317 - [c15]Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, Shin-ichiro Mori:
Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations. ISPAN 1994: 427-434 - 1993
- [j5]Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa:
A query-based parallel logic simulation algorithm. Syst. Comput. Jpn. 24(2): 11-21 (1993) - [c14]Xiao-ping Ling, Hideharu Amano:
Performance evaluation of WASMII: a data driven computer on a virtual hardware. PARLE 1993: 610-621 - [c13]Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi:
Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. SPDP 1993: 591-595 - 1992
- [c12]Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa:
A Parallel Logic Simulation Algorithm Based on Query. ICPP (3) 1992: 262-266 - [c11]Hideharu Amano, Luo Zhou, Kalidou Gaye:
SSS (Simple Serial Synchronized)-MIN: A Novel Multi Stage Interconnection Architecture for Multiprocessors. IFIP Congress (1) 1992: 571-577 - 1991
- [j4]Taisuke Boku, Tomohiro Kudoh, Hideharu Amano, Tetsuro Kimura:
NCC: A concurrent description language for scientific calculation on multiprocessors. Syst. Comput. Jpn. 22(12): 1-10 (1991) - [c10]Hideharu Amano, Kalidou Gaye:
A Batcher Double Omega Network with Combining. ICPP (1) 1991: 718-719 - 1990
- [j3]Hideharu Amano, Taisuke Boku, Tomohiro Kudoh:
(SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations. IEEE Trans. Computers 39(7): 889-905 (1990) - [c9]Hideharu Amano:
A Fault Tolerant Batcher Network. ICPP (1) 1990: 441-444
1980 – 1989
- 1989
- [c8]Hideharu Amano, Takuya Terasawa, Tomohiro Kudoh:
Cache with Synchronization Mechanism. IFIP Congress 1989: 1001-1006 - [c7]Jun Miyazaki, Kenji Takeda, Hideharu Amano, Hideo Aiso:
A New Version of a Parallel Production System Machine, MANJI-II. IWDM 1989: 317-330 - [c6]Xiao-ping Ling, Hideharu Amano:
A static scheduling system for a parallel machine (SM)2-II. PARLE (1) 1989: 118-135 - 1988
- [c5]Taisuke Boku, Shigehiro Nomura, Hideharu Amano:
IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation. ISCA 1988: 365-372 - 1987
- [c4]Jun Miyazaki, Hideharu Amano, Kenji Takeda, Hideo Aiso:
A Shared Memory Architecture for MANJI Production System Machine. IWDM 1987: 517-531 - 1986
- [j2]Takashi Yokota, Hideharu Amano, Hideo Aiso:
Dynamic fault recovery in mesh-connected parallel computers. Syst. Comput. Jpn. 17(7): 10-18 (1986) - [c3]Chizuko Saito, Hideharu Amano, Tomohiro Kudoh, Hideo Aiso:
An Adaptable Cluster Structure of (SM)²-II. CONPAR 1986: 53-60 - 1985
- [j1]Hideharu Amano, Junji Chikawa, Takaichi Yoshida, Hideo Aiso:
Performance analysis of parallel machines using multi-read memory. Syst. Comput. Jpn. 16(3): 29-37 (1985) - [c2]Hideharu Amano, Taisuke Boku, Tomohiro Kudoh, Hideo Aiso:
(SM)²-II: A New Version of the Sparse Matrix Solving Machine. ISCA 1985: 100-107 - 1983
- [c1]Hideharu Amano, Takaichi Yoshida, Hideo Aiso:
(SM)2: Sparse Matrix Solving Machine. ISCA 1983: 213-220
Coauthor Index
[c387] [j120] [j119] [j111] [j109] [c372] [c365] [j105] [j103] [c361] [c355] [c349] [c348] [j99] [j97] [c342] [c336] [j93] [c333] [c319] [j90] [c305] [c303] [c302] [c301] [j85] [j84] [j82] [c298] [c293] [c288] [c286] [c285] [c284] [c278] [j79] [j78] [j76] [j75] [c270] [c261] [c256] [c254] [c244] [c242] [c241] [j66] [j63] [c235] [c220] [c219] [c206] [c205] [c201] [c193] [c192] [j45] [j41] [j40] [j39] [c180] [c176] [c174] [p2] [p1] [c165] [c164] [c163] [c162] [j36] [j34] [c151] [c150] [c149] [c147] [c146] [c142] [c138] [c131] [c130] [c129] [j28] [j27] [c124] [c117] [c116] [c115] [j24] [c112] [c110] [c105] [c102] [j23] [j22] [j20] [c92] [c91] [c84] [c80] [c75] [c70] [c65] [c60] [c58] [c57] [c55] [c53]
[c387] [j120] [j109] [c372] [j103] [c361] [c348] [j99] [j97] [c345] [c336] [j93] [c335] [c333] [c327] [j90] [j89] [c306] [c305] [c302] [c301] [j85] [j84] [j82] [c298] [c293] [c288] [c286] [c285] [c284] [c281] [c278] [j79] [j78] [j76] [j75] [c270] [c261] [c259] [c256] [c254] [c244] [c243] [c242] [c241] [j66] [j63] [c235] [j58] [j55] [c220] [c219] [c218] [c217] [c209] [c206] [c205] [c202] [c201] [c198] [c195] [c193] [c192] [j41] [j40] [c180] [c176] [c174] [p2] [p1] [c165] [c164] [c163] [c162] [j36] [j34] [c156] [c151] [c150] [c149] [c148] [c146] [c142] [c138] [c131] [c130] [c129] [j28] [c124] [c117] [c115] [c112] [c110] [c102] [c94] [c91] [c84]
[j121] [j113] [c366] [c350] [c346] [c300] [c299] [j80] [c283] [c281] [c272] [c271] [j78] [j77] [j74] [j73] [c252] [c245] [c239] [c238] [c236] [c230] [c227] [c226] [j62] [j55] [c218] [c217] [c209] [c201] [c200] [c198] [c195] [c192] [r1] [j48] [j47] [j44] [j40] [c186] [c185] [c184] [c181] [c177] [c172] [c166] [c162] [c160] [c144] [c133] [c132]
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