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2020 – today
- 2023
[j117]Ryota Yasudo
, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Designing low-diameter interconnection networks with multi-ported host-switch graphs. Concurr. Comput. Pract. Exp. 35(11) (2023)- [j116]Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi:
A Compression Router for Low-Latency Network-on-Chip. IEICE Trans. Inf. Syst. 106(2): 170-180 (2023) - [j115]Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano:
RT-libSGM: FPGA-Oriented Real-Time Stereo Matching System with High Scalability. IEICE Trans. Inf. Syst. 106(3): 337-348 (2023) - [j114]Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano:
Parallel Implementation of CNN on Multi-FPGA Cluster. IEICE Trans. Inf. Syst. 106(7): 1198-1208 (2023) - [j113]Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano:
A Scalable Body Bias Optimization Method Toward Low-Power CGRAs. IEEE Micro 43(1): 49-57 (2023) - [j112]Aika Kamei, Hideharu Amano, Takuya Kojima, Daiki Yokoyama, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho:
A Variation-Aware MTJ Store Energy Estimation Model for Edge Devices With Verify-and-Retryable Nonvolatile Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 31(4): 532-542 (2023) - [c381]Ziquan Qin, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai:
Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board. COOL CHIPS 2023: 1-6 - [c380]Hideharu Amano:
Efficient FPGA Implementation of Amoeba-inspired SAT Solver with Feedback and Bounceback Control: Harnessing Variable-Level Parallelism for Large-Scale Problem Solving in Edge Computing. HEART 2023: 41-48 - [c379]Haris Gulzar, Muhammad Shakeel, Katsutoshi Itoyama, Kazuhiro Nakadai, Kenji Nishida, Hideharu Amano, Takeharu Eda:
FPGA based Power-Efficient Edge Server to Accelerate Speech Interface for Socially Assistive Robotics. SII 2023: 1-6 - 2022
- [j111]Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano:
The Implementation of a Hybrid Router and Dynamic Switching Algorithm on a Multi-FPGA System. IEICE Trans. Inf. Syst. 105-D(12): 2008-2018 (2022) - [j110]Naoya Niwa, Hideharu Amano, Michihiro Koibuchi:
Boosting the Performance of Interconnection Networks by Selective Data Compression. IEICE Trans. Inf. Syst. 105-D(12): 2057-2065 (2022) - [j109]Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai:
Weighted Least Square Filter for Improving the Quality of Depth Map on FPGA. Int. J. Netw. Comput. 12(2): 425-445 (2022) - [j108]Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems 90: 104471 (2022) - [j107]Takuya Kojima, Ayaka Ohwada, Hideharu Amano:
Mapping-Aware Kernel Partitioning Method for CGRAs Assisted by Deep Learning. IEEE Trans. Parallel Distributed Syst. 33(5): 1213-1230 (2022) - [c378]Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano:
Power Analysis of Directly-connected FPGA Clusters. COOL CHIPS 2022: 1-6 - [c377]Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano:
Body Bias Control on a CGRA based on Convex Optimization. COOL CHIPS 2022: 1-3 - [c376]Kohei Ito, Ryota Yasudo, Hideharu Amano:
Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches. FPL 2022: 143-147 - [c375]Morihiro Kuga, Masahiro Iida, Hideharu Amano:
FPL Demo: An FPGA-IP Prototype Chip for MEC devices. FPL 2022: 467 - [c374]Kaijie Wei, Yuki Kuno, Masatoshi Arai, Hideharu Amano:
RT-libSGM: An Implementation of a Real-time Stereo Matching System on FPGA. HEART 2022: 1-9 - [c373]Yuchen Chen, Kaijie Wei, Hiroaki Nishi, Hideharu Amano:
An Implementation of a 3D Image Filter for Motion Vector Generation on an FPGA Board. CANDAR 2022: 83-89 - [c372]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR 2022: 117-123 - [c371]Aoi Hiruma, Kensuke Iizuka, Hideharu Amano:
Toward a training of CNNs on a multi-FPGA system. CANDARW 2022: 229-235 - [c370]Zhongyang Hou, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai:
An FPGA off-loading of HARK sound source localization. CANDARW 2022: 236-240 - [c369]Pengyu Huang, Kaijie Wei, Hideharu Amano, Kaori Ohkoda, Masashi Aono:
Multi-board FPGA Implementation to Solve the Satisfiability Problem for Multi-Agent Path Finding in Smart Factory. CANDARW 2022: 406-410 - [c368]Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
A Message Passing Interface Library for High-Level Synthesis on Multi-FPGA Systems. MCSoC 2022: 45-52 - [c367]Zhou Yuqing, Naoya Niwa, Hideharu Amano:
Distance Aware Compression for Low Latency High Bandwidth Interconnection Network. MCSoC 2022: 361-367 - [c366]Kimiyoshi Usami, Daiki Yokoyama, Aika Kamei, Hideharu Amano:
Optimal switching time to minimize store energy in MTJ-based flip-flops under process and temperature variations. NorCAS 2022: 1-7 - [c365]Yoshiya Shikama, Michihiro Koibuchi, Hideharu Amano:
A Hardware Trojan Exploiting Coherence Protocol on NoCs. PDCAT 2022: 301-313 - [c364]Ayaka Ohwada, Takuya Kojima, Hideharu Amano:
An efficient compilation of coarse-grained reconfigurable architectures utilizing pre-optimized sub-graph mappings. PDP 2022: 1-9 - [c363]Shigeyuki Takano, Hideharu Amano:
Reconfiguration Cost for Reconfigurable Computing Architectures. SNPD-Summer 2022: 62-67 - 2021
- [j106]Takeharu Ikezoe, Takuya Kojima, Hideharu Amano:
Recovering Faulty Non-Volatile Flip Flops for Coarse-Grained Reconfigurable Architectures. IEICE Trans. Electron. 104-C(6): 215-225 (2021) - [j105]Kazuei Hironaka, Kensuke Iizuka, Miho Yamakura, Akram Ben Ahmed, Hideharu Amano:
Remote Dynamic Reconfiguration of a Multi-FPGA System FiC (Flow-in-Cloud). IEICE Trans. Inf. Syst. 104-D(8): 1321-1331 (2021) - [j104]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. IEICE Trans. Inf. Syst. 104-D(12): 2029-2039 (2021) - [j103]Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano:
CLAHE Implementation and Evaluation on a Low-End FPGA Board by High-Level Synthesis. IEICE Trans. Inf. Syst. 104-D(12): 2048-2056 (2021) - [j102]Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. IEICE Trans. Inf. Syst. 104-D(12): 2057-2067 (2021) - [j101]Miho Yamakura, Ryousei Takano, Akram Ben Ahmed, Midori Sugaya, Hideharu Amano:
A Multi-Tenant Resource Management System for Multi-FPGA Systems. IEICE Trans. Inf. Syst. 104-D(12): 2078-2088 (2021) - [j100]Kaijie Wei, Koki Honda, Hideharu Amano:
An implementation methodology for Neural Network on a Low-end FPGA Board. Int. J. Netw. Comput. 11(2): 172-197 (2021) - [j99]Ryota Yasudo, José Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo:
Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms. ACM Trans. Reconfigurable Technol. Syst. 14(3): 12:1-12:21 (2021) - [c362]Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
Implementing VTA, a tensor accelerator on Flow-in-Cloud. ACIT 2021: 46-50 - [c361]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT 2021: 51-55 - [c360]Hideto Kayashima, Hideharu Amano:
TCI Tester: Tester for Through Chip Interface. ASP-DAC 2021: 103-104 - [c359]Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano:
Hybrid Network of Packet Switching and STDM in a Multi-FPGA System. COOL CHIPS 2021: 1-6 - [c358]Sannomiya Natsuho, Takeshi Ohkawa, Hideharu Amano, Midori Sugaya:
Power Consumption Reduction Method and Edge Offload Server for Multiple Robots. EDGE 2021: 1-19 - [c357]Ying Jie Yan, Hideharu Amano, Masashi Aono, Kaori Ohkoda, Shingo Fukuda, Kenta Saito, Seiya Kasai:
Resource-saving FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim. FPT 2021: 1-5 - [c356]Hiroaki Suzuki, Wataru Takahashi, Kazutoshi Wakabayashi, Hideharu Amano:
A programming environment for multi-FPGA systems based on CyberWorkBench: an integrated design tool. HEART 2021: 5:1-5:6 - [c355]Naoya Niwa, Hideharu Amano, Michihiro Koibuchi:
Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression. CANDAR 2021: 56-64 - [c354]Takumi Inage, Kazuei Hironaka, Kensuke Iizuka, Kohei Ito, Yasuyu Fukushima, Mitaro Namiki, Hideharu Amano:
M-KUBOS/PYNQ Cluster for multi-access edge computing. CANDAR 2021: 95-101 - [c353]Hideto Kayashima, Hideharu Amano:
Analysis of Resistance Distribution and Voltage Drop in Chips with Inductive Coupling Wireless Communication Interface. CANDAR (Workshops) 2021: 292-296 - [c352]Renzhi Mao, Kaijie Wei, Hideharu Amano, Yuki Kuno, Masatoshi Arai:
Weight Least Square Filter for Improving the Quality of Depth Map on FPGA. CANDAR (Workshops) 2021: 297-300 - [c351]Yasuyu Fukushima, Kensuke Iizuka, Hideharu Amano:
Parallel Implementation of CNN on Multi-FPGA Cluster. MCSoC 2021: 77-83 - [c350]Aika Kamei, Takuya Kojima, Hideharu Amano, Daiki Yokoyama, Hisato Miyauchi, Kimiyoshi Usami, Keizo Hiraga, Kenta Suzuki, Kazuhiro Bessho:
Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops. MCSoC 2021: 273-280 - [c349]Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi:
A Case for Low-Latency Network-on-Chip using Compression Routers. PDP 2021: 134-142 - [c348]Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP 2021: 143-147 - 2020
- [j98]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. 103-D(1): 101-110 (2020) - [j97]Yuxi Sun, Hideharu Amano:
FiC-RNN: A Multi-FPGA Acceleration Framework for Deep Recurrent Neural Networks. IEICE Trans. Inf. Syst. 103-D(12): 2457-2462 (2020) - [j96]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. 103-D(12): 2471-2479 (2020) - [j95]Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano, Rodney Van Meter:
Extracting Success from IBM's 20-Qubit Machines Using Error-Aware Compilation. ACM J. Emerg. Technol. Comput. Syst. 16(3): 32:1-32:25 (2020) - [j94]Takuya Kojima, Nguyen Anh Vu Doan, Hideharu Amano:
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 28(11): 2383-2396 (2020) - [c347]M. M. Imdad Ullah, Akram Ben Ahmed, Hideharu Amano:
Implementation of FM-Index Based Pattern Search on a Multi-FPGA System. ARC 2020: 376-391 - [c346]Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda:
Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization. COOL CHIPS 2020: 1-3 - [c345]Ryuta Kawano, Hiroki Matsutani, Hideharu Amano:
Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. CANDAR (Workshops) 2020: 93-99 - [c344]Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa:
FPGA Acceleration of ROS2-Based Reinforcement Learning Agents. CANDAR (Workshops) 2020: 106-112 - [c343]Manfred Orsztynowicz, Hideharu Amano, Kenichi Kubota, Takaaki Miyajima:
Exploiting temporal parallelism in particle-based incompressive fluid simulation on FPGA. CANDAR 2020: 195-201 - [c342]Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano:
Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. CANDAR (Workshops) 2020: 211-217 - [c341]Kaijie Wei, Koki Honda, Hideharu Amano:
An implementation methodology for Neural Network on a Low-end FPGA Board. CANDAR 2020: 228-234 - [c340]Yugo Yamauchi, Akram Ben Ahmed, Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano:
Horizontal division of deep learning applications with all-to-all communication on a multi-FPGA system. CANDAR (Workshops) 2020: 277-281 - [c339]Koki Honda, Kaijie Wei, Masatoshi Arai, Hideharu Amano:
CLAHE implementation on a low-end FPGA board by high-level synthesis. CANDAR (Workshops) 2020: 282-285 - [c338]Daniel Pinheiro Leal, Midori Sugaya, Hideharu Amano, Takeshi Ohkawa:
Automated Integration of High-Level Synthesis FPGA Modules with ROS2 Systems. FPT 2020: 292-293 - [c337]Kensuke Iizuka, Kohei Ito, Kazuei Hironaka, Hideharu Amano:
A Method of Partitioning Convolutional Layer to Multiple FPGAs. ISOCC 2020: 25-26 - [c336]Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. PDP 2020: 102-109
2010 – 2019
- 2019
- [j93]Takuya Kojima, Hideharu Amano:
A Fine-Grained Multicasting of Configuration Data for Coarse-Grained Reconfigurable Architectures. IEICE Trans. Inf. Syst. 102-D(7): 1247-1256 (2019) - [j92]Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano:
Designing High-Performance Interconnection Networks with Host-Switch Graphs. IEEE Trans. Parallel Distributed Syst. 30(2): 315-330 (2019) - [c335]Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano:
Key-value Store Chip Design for Low Power Consumption. COOL CHIPS 2019: 1-3 - [c334]Yugo Yamauchi, Kazusa Musha, Hideharu Amano:
Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud. COOL CHIPS 2019: 1-3 - [c333]Michihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova:
Sparse 3-D NoCs with Inductive Coupling. DAC 2019: 49 - [c332]Takuya Kojima, Naoki Ando, Yusuke Matsushita, Hideharu Amano:
Demonstration of Low Power Stream Processing Using a Variable Pipelined CGRA. FPL 2019: 411-412 - [c331]Kazuei Hironaka, Kensuke Iizuka, Akram Ben Ahmed, M. M. Imdad Ullah, Yugo Yamauchi, Yuxi Sun, Miho Yamakura, Aoi Hiruma, Hideharu Amano:
Demonstration of Flow-in-Cloud: A Multi-FPGA System. FPL 2019: 417-418 - [c330]Hiroyuki Noda, Manfred Orsztynowicz, Kensuke Iizuka, Takaaki Miyajima, Naoyuki Fujita, Hideharu Amano:
An ARM-based heterogeneous FPGA accelerator for Hall thruster simulation. HEART 2019: 9:1-9:6 - [c329]Miho Yamakura, Kazuei Hironaka, Keita Azegami, Kazusa Musha, Hideharu Amano:
The Evaluation of Partial Reconfiguration for a Multi-board FPGA System FiCSW. HEART 2019: 15:1-15:4 - [c328]Yuxi Sun, Akram Ben Ahmed, Hideharu Amano:
Acceleration of Deep Recurrent Neural Networks with an FPGA cluster. HEART 2019: 18:1-18:4 - [c327]Ryuta Kawano, Hiroki Matsutani, Hideharu Amano:
Deadlock-Free Layered Routing for Infiniband Networks. CANDAR Workshops 2019: 84-90 - [c326]Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano:
Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process. CANDAR Workshops 2019: 269-274 - [c325]Ryosuke Kazami, Hideharu Amano:
A Rapid Optimization Method for Visual Indirect SLAM Using a Subset of Feature Points. CANDAR Workshops 2019: 275-279 - [c324]Yasuaki Okamoto, Hideharu Amano:
Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel. CANDAR Workshops 2019: 280-284 - [c323]Takeharu Ikezoe, Takuya Kojima, Hideharu Amano:
A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-Volatile Configurable Memory. FPT 2019: 81-89 - [c322]Hayate Okuhara, Ryosuke Kazami, Hideharu Amano:
A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration. MCSoC 2019: 32-37 - [c321]Koki Honda, Kaijie Wei, Hideharu Amano:
FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board. MCSoC 2019: 53-60 - [c320]Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki:
A Preliminary Evaluation of Building Block Computing Systems. MCSoC 2019: 312-319 - [c319]Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano:
A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System. MCSoC 2019: 328-333 - [c318]Takuya Kojima, Hideharu Amano:
Refinements in Data Manipulation Method for Coarse Grained Reconfigurable Architectures. ReCoSoC 2019: 113-120 - [c317]Kazuei Hironaka, Akram Ben Ahmed, Hideharu Amano:
Multi-FPGA Management on Flow-in-Cloud Prototype System. SNPD 2019: 443-448 - [i2]Shin Nishio, Yulu Pan, Takahiko Satoh, Hideharu Amano, Rodney Van Meter:
Extracting Success from IBM's 20-Qubit Machines Using Error-Aware Compilation. CoRR abs/1903.10963 (2019) - 2018
- [j91]Carlos Cesar Cortes Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano:
Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach. IEICE Trans. Inf. Syst. 101-D(4): 1116-1125 (2018) - [j90]Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano:
Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures. IEICE Trans. Inf. Syst. 101-D(6): 1532-1540 (2018) - [j89]Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. IEICE Trans. Inf. Syst. 101-D(9): 2258-2268 (2018) - [j88]Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano:
Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Int. J. Netw. Comput. 8(1): 124-139 (2018) - [j87]Hayate Okuhara, Akram Ben Ahmed, Hideharu Amano:
Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(10): 3241-3254 (2018) - [j86]Keita Azegami, Hayate Okuhara, Hideharu Amano:
Body Bias Control for Renewable Energy Source with a High Inner Resistance. IEEE Trans. Multi Scale Comput. Syst. 4(4): 605-612 (2018) - [j85]Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano:
Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1254-1267 (2018) - [c316]Kazusa Musha, Tomohiro Kudoh, Hideharu Amano:
Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud. ARC 2018: 43-54 - [c315]Kazuei Hironaka, Ng. Anh Vu Doan, Hideharu Amano:
Towards an Optimized Multi FPGA Architecture with STDM Network: A Preliminary Study. ARC 2018: 142-150 - [c314]Ryosuke Kazami, Hayate Okuhara, Hideharu Amano:
Design automation methodology of a critical path monitor for adaptive voltage controls. COOL CHIPS 2018: 1-3 - [c313]Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Hiroyuki Noda, Hideharu Amano:
Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC. DDECS 2018: 55-60 - [c312]Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano:
Performance Prediction for Large-Scale Heterogeneous Platforms. FCCM 2018: 220 - [c311]Takuya Kojima, Hideharu Amano:
A Configuration Data Multicasting Method for Coarse-Grained Reconfigurable Architectures. FPL 2018: 239-242 - [c310]Hideharu Amano:
Accelerator-in-Switch: A Novel Cooperation Framework for FPGAs and GPUs. FPT 2018: 22 - [c309]Ryota Yasudo, José Gabriel F. Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker:
Performance Estimation for Exascale Reconfigurable Dataflow Platforms. FPT 2018: 314-317 - [c308]Kaijie Wei, Koki Honda, Hideharu Amano:
FPGA Design for Autonomous Vehicle Driving Using Binarized Neural Networks. FPT 2018: 425-428 - [c307]Takuya Kojima, Naoki Ando, Yusuke Matshushita, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano:
Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping. HEART 2018: 13:1-13:6 - [c306]Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano:
k-Optimized Path Routing for High-Throughput Data Center Networks. CANDAR 2018: 99-105 - [c305]Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. CANDAR Workshops 2018: 182-185 - [c304]Hideki Shimura, Hiroyuki Noda, Hideharu Amano:
C4: An FPGA-based Compression Algorithm for ExpEther. CANDAR Workshops 2018: 356-362 - [c303]Tomohiro Totoki, Michihiro Koibuchi, Hideharu Amano:
An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking. CANDAR Workshops 2018: 363-369 - [c302]