default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDHOST 2018: Washington, DC, USA
- 2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, Washington, DC, USA, April 30 - May 4, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-4731-8
- Nader Sehatbakhsh
, Monjur Alam, Alireza Nazari, Alenka G. Zajic, Milos Prvulovic:
Syndrome: Spectral analysis for anomaly detection on medical IoT and embedded devices. 1-8 - Xavier Carpent, Norrathep Rattanavipanon, Gene Tsudik:
Remote attestation of IoT devices via SMARM: Shuffled measurements against roving malware. 9-16 - Mengmei Ye, Jonathan Sherman, Witawas Srisa-an, Sheng Wei:
TZSlicer: Security-aware dynamic program slicing for hardware isolation. 17-24 - Nikolay Matyunin, Jakub Szefer, Stefan Katzenbeisser:
Zero-permission acoustic cross-device tracking. 25-32 - Robert Specht, Vincent Immler, Florian Unterstein, Johann Heyszl, Georg Sigl:
Dividing the threshold: Multi-probe localized EM analysis on threshold implementations. 33-40 - Jacob Couch, Nicole Whewell, Andrew Monica, Stergios Papadakis:
Direct read of idle block RAM from FPGAs utilizing photon emission microscopy. 41-48 - Vincent Immler, Johannes Obermaier, Martin König, Matthias Hiller, Georg Sigl:
B-TREPID: Batteryless tamper-resistant envelope with a PUF and integrity detection. 49-56 - Yuan Yao, Mo Yang, Conor Patrick, Bilgiday Yuce, Patrick Schaumont:
Fault-assisted side-channel analysis of masked implementations. 57-64 - Elena Dubrova, Maxim Teslenko:
An efficient SAT-based algorithm for finding short cycles in cryptographic algorithms. 65-72 - Michael Tempelmeier, Fabrizio De Santis, Georg Sigl, Jens-Peter Kaps:
The CAESAR-API in the real world - Towards a fair evaluation of hardware CAESAR candidates. 73-80 - Aydin Aysu, Youssef Tobah, Mohit Tiwari, Andreas Gerstlauer, Michael Orshansky:
Horizontal side-channel vulnerabilities of post-quantum key exchange protocols. 81-88 - Preeti Kumari, Bashir M. Sabquat Bahar Talukder, Sadman Sakib, Biswajit Ray, Md. Tauhidur Rahman:
Independent detection of recycled flash memory: Challenges and solutions. 89-95 - Prashanth Mohan, Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai:
A compact energy-efficient pseudo-static camouflaged logic family. 96-102 - Asmit De, Anirudh Iyengar, Mohammad Nasim Imtiaz Khan, Sung-Hao Lin, Sandeep Krishna Thirumala, Swaroop Ghosh, Sumeet Kumar Gupta:
CTCG: Charge-trap based camouflaged gates for reverse engineering prevention. 103-110 - Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai:
Secure chip odometers using intentional controlled aging. 111-117 - Xiaodan Xi, Aydin Aysu, Michael Orshansky:
Fresh re-keying with strong PUFs: A new approach to side-channel security. 118-125 - Robert Hesselbarth, Florian Wilde, Chongyan Gu, Neil Hanley:
Large scale RO PUF analysis over slice type, evaluation time and temperature on 28nm Xilinx FPGAs. 126-133 - Junko Takahashi, Masashi Tanaka, Hitoshi Fuji, Toshio Narita, Shunsuke Matsumoto, Hiroki Sato:
Abnormal vehicle behavior induced using only fabricated informative CAN messages. 134-137 - Athanassios Moschos, Apostolos P. Fournaris, Odysseas G. Koufopavlou:
A flexible leakage trace collection setup for arbitrary cryptographic IP cores. 138-142 - Md. Badruddoja Majumder, Md Sakib Hasan, Mesbah Uddin, Garrett S. Rose:
Chaos computing for mitigating side channel attack. 143-146 - William Diehl, Abubakr Abdulgadir, Farnoud Farahmand, Jens-Peter Kaps, Kris Gaj:
Comparison of cost of protection against differential power analysis of selected authenticated ciphers. 147-152 - Wenjie Che, Manel Martínez-Ramón, Fareena Saqib, Jim Plusquellic:
Delay model and machine learning exploration of a hardware-embedded delay PUF. 153-158 - Arvind Singh, Nikhil Chawla, Monodeep Kar, Saibal Mukhopadhyay:
Energy efficient and side-channel secure hardware architecture for lightweight cipher SIMON. 159-162 - Zhiming Zhang, Qiaoyan Yu, Laurent Njilla, Charles A. Kamhoua:
FPGA-oriented moving target defense against security threats from malicious FPGA tools. 163-166 - Kai Yang, Jungmin Park, Mark Tehranipoor, Swarup Bhunia:
Hardware virtualization for protection against power analysis attack. 167-172 - Subhadeep Banik, Andrey Bogdanov, Francesco Regazzoni, Takanori Isobe, Harunaga Hiwatari, Toru Akishita:
Inverse gating for low energy encryption. 173-176 - Patrick Cronin, Chengmo Yang:
Lowering the barrier to online malware detection through low frequency sampling of HPCs. 177-180 - Richa Agrawal, Ranga Vemuri:
On state encoding against power analysis attacks for finite state controllers. 181-186 - Hongyu Fang, Sai Santosh Dayapule, Fan Yao, Milos Doroslovacki, Guru Venkataramani:
Prefetch-guard: Leveraging hardware prefetches to defend against cache timing channels. 187-190 - Anubhab Baksi, Shivam Bhasin, Jakub Breier, Mustafa Khairallah, Thomas Peyrin:
Protecting block ciphers against differential fault attacks without re-keying. 191-194 - Yumin Hou, Hu He, Kaveh Shamsi, Yier Jin, Dong Wu, Huaqiang Wu:
R2D2: Runtime reassurance and detection of A2 Trojan. 195-200 - Adam Duncan, Lei Jiang, Martin Swany:
Repurposing SoC analog circuitry for additional COTS hardware security. 201-204 - Baibhab Chatterjee, Debayan Das, Shreyas Sen:
RF-PUF: IoT security enhancement through authentication of wireless nodes using in-situ machine learning. 205-208 - Mahabubul Alam, Sreeja Chowdhury, Mark Tehranipoor, Ujjwal Guin:
Robust, low-cost, and accurate detection of recycled ICs using digital signatures. 209-214 - Shahrzad Keshavarz, Falk Schellenberg, Bastian Richter, Christof Paar, Daniel E. Holcomb:
SAT-based reverse engineering of gate-level schematics using fault injection and probing. 215-220 - Goutham Pocklassery, Wenjie Che, Fareena Saqib, Matthew Areno, Jim Plusquellic:
Self-authenticating secure boot for FPGAs. 221-226 - Tao Liu, Wujie Wen, Yier Jin:
SIN2: Stealth infection on neural network - A low-cost agile neural Trojan attack methodology. 227-230 - Hongxiang Gu, Miodrag Potkonjak:
Securing interconnected PUF network with reconfigurability. 231-234 - Rami Sheikh, Ro Cammarota, Wenjia Ruan:
Value prediction for security (VPsec): Countering fault attacks in modern microprocessors. 235-238
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-12 22:52 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
