default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIMS 2000: Cambridge, MA, USA
- Frederic T. Chong, Christoforos E. Kozyrakis, Mark Oskin:
Intelligent Memory Systems, Second International Workshop, IMS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers. Lecture Notes in Computer Science 2107, Springer 2001, ISBN 3-540-42328-1
Memory Technology
- Junji Ogawa, Mark Horowitz:
A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. 1-14 - Hiroshi Nakamura
, Masaaki Kondo, Taisuke Boku:
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. 15-32
Processor and Memory Architecture
- Robert Cooksey, Dennis Colarelli, Dirk Grunwald:
Content-Based Prefetching: Initial Results. 33-55 - Lixin Zhang, Venkata K. Pingali, Bharat Chandramouli, John B. Carter:
Memory System Support for Dynamic Cache Line Assembly. 56-70 - Yan Solihin, Jaejin Lee, Josep Torrellas:
Adaptively Mapping Code in an Intelligent Memory Architecture. 71-84
Applications and Operating Systems
- Richard C. Murphy, Peter M. Kogge, Arun Rodrigues:
The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems. 85-103 - Mary W. Hall, Craig S. Steele:
Memory Management in a PIM-Based Architecture. 104-121
Compiler Technology
- David Judd, Katherine A. Yelick, Christoforos E. Kozyrakis, David R. Martin, David A. Patterson:
Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler. 122-134 - Csaba Andras Moritz, Matthew I. Frank, Saman P. Amarasinghe:
FlexCache: A Framework for Flexible Compiler Generated Data Caching. 135-146
Poster Session
- Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
Aggressive Memory-Aware Compilation. 147-151 - Michael C. Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas:
Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. 152-159 - Tsung-Chuan Huang, Slo-Li Chu:
SAGE: A New Analysis and Optimization System for FlexRAM Architecture. 160-168 - Koji Inoue, Koji Kai, Kazuaki J. Murakami:
Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems. 169-178 - Jeff La Coss:
The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems. 179-182 - Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta:
Compiler-Directed Cache Line Size Adaptivity. 183-187 - Workshop Notes. 188-192
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-10-30 00:37 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
