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ORCID43rd ISMVL 2013: Toyama, Japan
- 43rd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2013, Toyama, Japan, May 22-24, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-6067-8
- Yutaka Hata, Hiroshi Nakajima:
Computational Medical and Health Care Technology. 1-5 - Hiroshi Nakajima, Toshikazu Shiga, Yutaka Hata:
Systems Health Care: Health Management Technology. 6-11 - Tatsuhiro Fujimoto, Hiroshi Nakajima, Naoki Tsuchiya, Hideya Marukawa, Kei Kuramoto, Syoji Kobashi
, Yutaka Hata:
Wearable Human Activity Recognition by Electrocardiograph and Accelerometer. 12-17 - Mingmin Yan, Hiroki Tamura, Koichi Tanno:
Gaze Estimation Using Electrooculogram Signals and Its Mathematical Modeling. 18-22 - Koki Tsukuda, Tadahito Egawa, Kazuhiko Taniguchi, Kei Kuramoto, Syoji Kobashi, Yutaka Hata:
Fuzzy Damage Extraction Method for Ultrasonic Nondestructive Testing Images. 23-28 - Robert Wille, Hongyan Zhang, Rolf Drechsler:
Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits. 29-34 - Ben Schaeffer, Linh Tran, Addison Gronquist, Marek A. Perkowski, Pawel Kerntopf:
Synthesis of Reversible Circuits Based on Products of Exclusive OR Sums. 35-40 - Maher Hawash, Martin Lukac, Michitaka Kameyama, Marek A. Perkowski:
Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format. 41-46 - Chander Chandak, Anupam Chattopadhyay, Soumajit Majumder, Subhamoy Maitra:
Analysis and Improvement of Transformation-Based Reversible Logic Synthesis. 47-52 - Takahiro Takeda, Kei Kuramoto, Syoji Kobashi, Yutaka Hata:
A Fuzzy Human Detection for Security System Using Infrared Laser Camera. 53-58 - Masato Kuki, Hiroshi Nakajima, Naoki Tsuchiya, Kei Kuramoto, Syoji Kobashi, Yutaka Hata:
Mining Multi Human Locations Using Thermopile Array Sensors. 59-64 - Naotake Kamiura, Tomoya Fukuda, Ayumu Saitoh, Teijiro Isokawa, Nobuyuki Matsui, Hitoshi Tabuchi:
On Selection of Intraocular Power Formula Using Support Vector Machines and Genetic Algorithm. 65-70 - Noboru Takagi, Jianjun Chen:
A Broken Line Classification Method of Mathematical Graphs for Automating Translation into Scalable Vector Graphic. 71-76 - Marek A. Perkowski, Aditya Bhutada, Martin Lukac, Mathias Sunardi:
On Synthesis and Verification from Event Diagrams in a Robot Theatre Application. 77-83 - Stanislav Stankovic, Radomir S. Stankovic, Jaakko Astola:
Remarks on Applications of Shapes of Decision Diagrams in Classification of Multiple-Valued Logic Functions. 84-89 - Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions. 90-95 - Tsutomu Sasao:
An Application of Autocorrelation Functions to Find Linear Decompositions for Incompletely Specified Index Generation Functions. 96-102 - Mitchell A. Thornton:
A Transfer Function Model for Ternary Switching Logic Circuits. 103-108 - Mitchell A. Thornton, Theodore W. Manikas:
Spectral Response of Ternary Logic Netlists. 109-116 - Hajime Machida, Ivo G. Rosenberg:
A Study on Essentially Minimal Clones. 117-122 - Miguel Couceiro, Lucien Haddad, Karsten Schölzel, Tamás Waldhauser:
A Solution to a Problem of D. Lau: Complete Classification of Intervals in the Lattice of Partial Boolean Clones. 123-128 - Dmitriy Zhuk, Stanislav Moiseev:
On the Clones Containing a Near-Unanimity Function. 129-134 - Lucien Haddad, Karsten Schölzel:
Intersections with Slupecki Partial Clones on a Finite Set. 135-140 - Boris A. Romov:
Not Finitely Definable Partial Clones on a Finite Set. 141-145 - Masanori Natsui, Kiyohiro Kashiuchi, Takahiro Hanyu:
Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications. 146-151 - Yuki Kurisu, Tatsuya Sasaki, Takao Waho:
A Successive Approximation A/D Converter Using Generalized Non-Binary Algorithm. 152-157 - Kotaro Okamoto, Naofumi Homma, Takafumi Aoki:
A Graph-Based Approach to Designing Parallel Multipliers over Galois Fields Based on Normal Basis Representations. 158-163 - Xu Bai, Michitaka Kameyama:
Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI. 164-169 - Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Mojtaba Maleknejad, Keivan Navi, Omid Hashemipour:
Dramatically Low-Transistor-Count High-Speed Ternary Adders. 170-175 - Martin Goldstern:
The Complexity of Lukasiewicz Logic. 176-181 - Jelena Colic, Hajime Machida, Jovanka Pantovic:
On Hyper Co-Clones. 182-185 - Sebastian Kerkhoff, Friedrich Martin Schneider:
Clones of Partial Cofunctions. 186-191 - Andrei A. Bulatov:
Boolean Max-Co-Clones. 192-197 - Tsutomu Sasao:
Four Decades of Multi-Valued Logic: Lists of Highly Cited Papers. 198-202 - Cheng-Hung Chen, Rong-Zuo Jhang, Yen-Yun Liao:
Chaotic Time Series Prediction Using Neuro-Fuzzy Systems with Cluster-Based Tribes Optimization Algorithm. 203-208 - Mayuka F. Kawaguchi, Kouta Minami, Michiro Kondo:
Join Operations on Commutative BCK-Algebras with Condition (S). 209-211 - Hiromitsu Kimura, Zhiyong Zhong, Yuta Mizuochi, Norihiro Kinouchi, Yoshinobu Ichida, Yoshikazu Fujimori:
Highly Reliable Non-Volatile Logic Circuit Technology and Its Application. 212-218 - Ivan Chajda, Jan Paseka:
Tense Operators and Dynamic De Morgan Algebras. 219-224 - Dan A. Simovici:
On the Combinatorics of Tolerance Relations. 225-230 - Norihiro Kamide:
On Natural Eight-Valued Reasoning. 231-236 - Norihiro Kamide:
Embedding-Based Methods for Trilattice Logic. 237-242 - Jorge Almeida, Miguel Couceiro, Tamás Waldhauser:
On the Semigroup of Equational Classes of Finite Functions. 243-247 - Mostafa Rashdan, James W. Haslett:
Comparing Performance of a Multiple-Valued Time-Based Serial Data Link with Other Serial Links. 248-253 - Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet:
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating. 254-259 - Arif Abdul Mannan, Koichi Tanno, Hiroki Tamura, Takako Toyama, Agung Darmawansyah:
Expandable MVL Inverter Compatible with Standard CMOS Process and Its Application to MVL Hysteresis Comparator. 260-265 - Takahiro Hanyu, Yuma Watanabe, Atsushi Matsumoto:
Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information. 266-271 - Xu Bai, Michitaka Kameyama:
An Area-Efficient Multiple-Valued Reconfigurable VLSI Architecture Using an X-Net. 272-277 - Golam Tangim, Svetlana N. Yanushkevich, Seiya Kasai, Vlad P. Shmerko:
Noise-Tolerant Model of a Ternary Inverter Based on Markov Random Field. 278-283 - Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems. 284-289 - Nan Li, Shohreh Sharif Mansouri, Elena Dubrova:
Secure Key Storage Using State Machines. 290-295 - Dusan B. Gajic, Radomir S. Stankovic:
The Impact of Address Arithmetic on the GPU Implementation of Fast Algorithms for the Vilenkin-Chrestenson Transform. 296-301 - Bernd Steinbach, Christian Posthoff:
Solution of the Last Open Four-Colored Rectangle-Free Grid: An Extremely Complex Multiple-Valued Problem. 302-309 - Mitchell A. Thornton, Jennifer Dworak:
Ternary Logic Network Justification Using Transfer Matrices. 310-315 - Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler:
Debugging of Reversible Circuits Using pDDs. 316-321 - Martin Lukac, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf:
Analysis of Reversible and Quantum Finite State Machines Using Homing, Synchronizing and Distinguishing Input Sequences. 322-327 - Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler:
Exact Template Matching Using Boolean Satisfiability. 328-333 - Bikromadittya Mondal, Pradyut Sarkar, Pranay Kumar Saha, Susanta Chakraborty:
Synthesis of Balanced Ternary Reversible Logic Circuit. 334-339 - Claudio Moraga, Milena Stankovic, Radomir S. Stankovic, Suzana Stojkovic:
Contribution to the Study of Multiple-Valued Bent Functions. 340-345 - Milan Petrík, Mirko Navara, Peter Sarkoci:
Alternative Proof of Mulholland's Theorem and New Solutions to Mulholland Inequality. 346-351
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