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ORCID36th MICRO 2003: San Diego, CA, USA
- Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003. IEEE Computer Society 2003, ISBN 0-7695-2043-X
- Kerry Bernstein:
Microarchitecture on the MOSFET Diet. 3-6 - Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge:
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. 7-18 - Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy:
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. 19-28 - Shubhendu S. Mukherjee, Christopher T. Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin:
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor. 29-42 - Bradford M. Beckmann, David A. Wood:
TLC: Transmission Line Caches. 43-54 - Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar:
Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures. 55-66 - Se-Hyun Yang, Babak Falsafi:
Near-Optimal Precharging in High-Performance Nanoscale CMOS Caches. 67-80 - Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
:
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. 81-92 - Canturk Isci, Margaret Martonosi:
Runtime Power Monitoring in High-End Processors: Methodology and Empirical Data. 93-104 - Hangsheng Wang, Li-Shiuan Peh, Sharad Malik:
Power-driven Design of Router Microarchitectures in On-chip Networks. 105-116 - Allan Hartstein, Thomas R. Puzak:
Optimum Power/Performance Pipeline Depth. 117-128 - Nathan Clark, Hongtao Zhong, Scott A. Mahlke:
Processor Acceleration Through Automated Instruction Set Customization. 129-140 - Silviu M. S. A. Chiricescu, Ray Essick, Brian Lucas, Phil May, Kent Moat, Jim Norris, Michael A. Schuette, Ali Saidi:
The Reconfigurable Streaming Vector Processor (RSVPTM). 141-150 - Richard A. Hankins, Trung A. Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John Paul Shen:
Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice. 151-164 - Michael S. Schlansker:
In Memory of Bob Rau. 165-168 - Kim M. Hazelwood, Michael D. Smith:
Generational Cache Management of Code Traces in Dynamic Optimization Systems. 169-179 - Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung Yew, Dong-yuan Chen:
The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System. 180-190 - Leonid Baraz, Tevi Devor, Orna Etzion, Shalom Goldenberg, Alex Skaletsky, Yun Wang, Yigel Zemach:
IA-32 Execution Layer: a two-phase dynamic translator designed to support IA-32 applications on Itanium-based systems. 191-204 - Vikram S. Adve, Chris Lattner, Michael Brukman, Anand Shukla, Brian Gaeke:
LLVA: A Low-level Virtual Instruction Set Architecture. 205-216 - Ashutosh S. Dhodapkar, James E. Smith:
Comparing Program Phase Detection Techniques. 217-227 - Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn:
Using Interaction Costs for Microarchitectural Bottleneck Analysis. 228-242 - Daniel A. Jiménez:
Fast Path-Based Neural Branch Prediction. 243-252 - Ho-Seop Kim, James E. Smith:
Hardware Support for Control Transfers in Code Caches. 253-264 - Saisanthosh Balakrishnan, Gurindar S. Sohi:
Exploiting Value Locality in Physical Register Files. 265-276 - Ilhyun Kim, Mikko H. Lipasti:
Macro-op Scheduling: Relaxing Scheduling Loop Constraints. 277-290 - Steven Swanson, Ken Michelson, Andrew Schwerin, Mark Oskin:
WaveScalar. 291-302 - Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger:
Universal Mechanisms for Data-Parallel Architectures. 303-314 - Enric Gibert, F. Jesús Sánchez, Antonio González:
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. 315-325 - Alex Aletà, Josep M. Codina, Antonio González, David R. Kaeli:
Instruction Replication for Clustered Microarchitectures. 326-338 - G. Edward Suh, Dwaine E. Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas:
Efficient Memory Integrity Verification and Encryption for Secure Processors. 339-350 - Jun Yang, Youtao Zhang, Lan Gao:
Fast Secure Processor for Inhibiting Software Piracy and Tampering. 351-360 - Stefanos Kaxiras, Georgios Keramidas:
IPStash: a Power-Efficient Memory Architecture for IP-lookup. 361-372 - Jorge García-Vidal, Jesús Corbal, Llorenç Cerdà, Mateo Valero:
Design and Implementation of High-Performance Memory Systems for Future Packet Buffers. 373-386 - Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu:
Beating in-order stalls with "flea-flicker" two-pass pipelining. 387-398 - Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler:
Scalable Hardware Memory Disambiguation for High ILP Processors. 399-410 - Il Park, Chong-liang Ooi, T. N. Vijaykumar:
Reducing Design Complexity of the Load/Store Queue. 411-422 - Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan:
Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors. 423-
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