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ORCID29th MICRO 1996: Paris, France
- Stephen W. Melvin, Steve Beaty:
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996. ACM/IEEE Computer Society 1996, ISBN 0-8186-7641-8 - Thomas M. Conte
, Sumedh W. Sathaye, Sanjeev Banerjia:
A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. 4-13 - James O. Bondi, Ashwini K. Nanda, Simonjit Dutta:
Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. 14-23 - Eric Rotenberg, Steve Bennett, James E. Smith:
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. 24-35 - Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch:
Accurate and Practical Profile-driven Compilation Using the Profile Buffer. 36-45 - Thomas Ball, James R. Larus:
Efficient Path Profiling. 46-57 - Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker:
Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. 58-67 - Brian L. Deitrich, Wen-mei W. Hwu:
Speculative Hedge: Regulating Compile-time Speculation Against Profile Variations. 70-79 - Robert S. Cohn, P. Geoffrey Lowney:
Hot Cold Optimization of Large Windows/NT Applications. 80-89 - Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, Wen-mei W. Hwu:
Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results. 90-99 - Richard Johnson, Michael S. Schlansker:
Analysis Techniques for Predicated Code. 100-113 - David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker:
Global Predicate Analysis and Its Application to Register Allocation. 114-125 - Daniel M. Lavery, Wen-mei W. Hwu:
Modulo Scheduling of Loops in Control-intensive Non-numeric Programs. 126-137 - Erik Jacobsen, Eric Rotenberg, James E. Smith:
Assigning Confidence to Conditional Branch Predictions. 142-152 - Scott A. Mahlke, Balas K. Natarajan:
Compiler Synthesized Dynamic Branch Prediction. 153-164 - Jim Pierce, Trevor N. Mudge:
Wrong-path Instruction Prefetching. 165-175 - Robert Yung:
Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture. 178-190 - Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt:
Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. 191-200 - Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye:
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. 201-211 - Shlomit S. Pinter, Adi Yoaz:
Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors. 214-225 - Mikko H. Lipasti, John Paul Shen:
Exceeding the Dataflow Limit via Value Prediction. 226-237 - Yiannakis Sazeides, Stamatis Vassiliadis, James E. Smith:
The Performance Potential of Data Dependence Speculation & Collapsing. 238-247 - Josep Llosa, Mateo Valero, Eduard Ayguadé:
Heuristics for Register-Constrained Software Pipelining. 250-261 - Mark G. Stoodley, Corinna G. Lee:
Software Pipelining Loops with Conditional Branches. 262-273 - Michael E. Wolf, Dror E. Maydan, Ding-Kai Chen:
Combining Loop Transformations Considering Caches and Scheduling. 274-286 - Eric Schnarr, James R. Larus:
Instruction Scheduling and Executable Editing. 288-297 - David A. Dunn, Wei-Chung Hsu:
Instruction Scheduling for the HP PA-8000. 298-307 - Santosh G. Abraham, Vinod Kathail, Brian L. Deitrich:
Meld Scheduling: Relaxing Scheduling Constraints Across Region Boundaries. 308-321 - Joseph A. Fisher, Paolo Faraboschi, Giuseppe Desoli:
Custom-fit Processors: Letting Applications Define Architectures. 324-335 - Anne M. Holler:
Optimization for a Superscalar Out-of-Order Machine. 336-348 - John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau:
Optimization of Machine Descriptions for Efficient Use. 349-358
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