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ORCID11th MTV 2010: Austin, TX, USA
- Magdy S. Abadir, Jay Bhadra, Li-C. Wang:
11th International Workshop on Microprocessor Test and Verification, MTV 2010, Austin, TX, USA, December 13-15, 2010. IEEE Computer Society 2010, ISBN 978-0-7695-4354-3
Session A
- Görschwin Fey
, André Sülflow, Rolf Drechsler:
Towards Unifying Localization and Explanation for Automated Debugging. 3-8 - Brian Keng, Andreas G. Veneris, Sean Safarpour:
An Automated Framework for Correction and Debug of PSL Assertions. 9-12
Session B
- Devraj Kallappa Bakchowde, Nanda Kishore A. S.:
An Efficient Event Generation Method for Testing a SOC with Multiple Processing Elements and Associated Peripherals. 15-18
Session C
- Wei Sheng, Yanyan Gao, Li Xi, Xuehai Zhou:
Schedulability Analysis for MultiCore Global Scheduling with Model Checking. 21-26
Session D
- Mauricio de Carvalho, Paolo Bernardi, Ernesto Sánchez, Matteo Sonza Reorda:
An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization. 29-34 - Hoang Minh Le, Daniel Große, Rolf Drechsler:
Automatic Fault Localization for SystemC TLM Designs. 35-40
Session E
- Oscar Ballan, Paolo Bernardi, Giovanni Fontana, Michelangelo Grosso, Ernesto Sánchez:
A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-Chip. 43-46 - Ouiza Dahmoune, Robert de B. Johnston:
An Embedded Reachability Analyzer and Invariant Checker (ERAIC). 47-50
Session F
- Nathan Buchanan, Hiren D. Patel:
Towards a Multi-MoC Hardware/Software Co-design Framework Using Abstract State Machines. 53-58
Session G
- Christian Miller, Karina Gitina, Christoph Scholl, Bernd Becker:
Bounded Model Checking of Incomplete Networks of Timed Automata. 61-66 - Padmaraj Singh, David L. Landis:
Test Generation for CMP Designs. 67-70
Special Session on Industry Innovation
- Alper Sen, Baris Aksanli, Murat Bozkurt:
Using Graphics Processing Units for Logic Simulation of Electronic Designs. 73-76
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