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ORCIDGörschwin Fey
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- affiliation: Hamburg University of Technology (TUHH), Institute of Embedded Systems, Germany
- affiliation: University of Bremen, Institute of Computer Science, Germany
- affiliation: German Aerospace Center (DLR), Bremen, Germany
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2020 – today
- 2020
[c128]Gianluca Martino, Heinz Riener, Görschwin Fey
:
Revisiting Explicit Enumeration for Exact Synthesis. DSD 2020: 29-34
2010 – 2019
- 2019
- [j21]Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Könighofer, Ingo Pill, Heinz Riener, Franz Röck:
Synthesizing adaptive test strategies from temporal logic specifications. Formal Methods Syst. Des. 55(2): 103-135 (2019) - [c127]Fin Hendrik Bahnsen, Görschwin Fey:
Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks. DSD 2019: 485-491 - [c126]Görschwin Fey, Alberto García Ortiz:
Symbolic Circuit Analysis under an Arc Based Timing Model. ETS 2019: 1-2 - [c125]Gianluca Martino, Görschwin Fey:
Syntax-Guided Enumeration of Temporal Properties. FDL 2019: 1-8 - [c124]Fin Hendrik Bahnsen, Görschwin Fey:
Approximation of Neural Networks for Verification. MBMV 2019: 1-10 - [c123]Görschwin Fey, Rolf Drechsler:
Self-Explaining Digital Systems - Some Technical Steps. MBMV 2019: 1-8 - [c122]Tara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik:
Engineering of an Effective Automatic Dynamic Assertion Mining Platform. VLSI-SoC 2019: 111-116 - 2018
- [c121]Abraham Temesgen Tibebu, Görschwin Fey:
Augmenting All Solution SAT Solving for Circuits with Structural Information. DDECS 2018: 117-122 - [c120]Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Görschwin Fey:
Software-Level TMR Approach for On-Board Data Processing in Space Applications. DDECS 2018: 147-152 - [c119]Jan Malburg, Heinz Riener, Görschwin Fey:
Mining Latency Guarantees for RTL Designs. ISMVL 2018: 68-73 - [c118]Rolf Drechsler, Christoph Lüth, Görschwin Fey, Tim Güneysu:
Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation. IVSW 2018: 1-6 - [c117]Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener:
Design Understanding: From Logic to Specification*. VLSI-SoC 2018: 172-175 - [i3]Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Könighofer, Ingo Pill, Heinz Riener, Franz Röck:
Synthesizing Adaptive Test Strategies from Temporal Logic Specifications. CoRR abs/1809.01607 (2018) - 2017
- [j20]Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey:
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. J. Electron. Test. 33(1): 53-64 (2017) - [j19]Gökçe Aydos, Görschwin Fey:
Empirical results on parity-based soft error detection with software-based retry. Microprocess. Microsystems 48: 62-68 (2017) - [j18]Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey:
metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. 19(5): 605-621 (2017) - [c116]Jan Malburg, Tino Flenker, Görschwin Fey:
Property mining using dynamic dependency graphs. ASP-DAC 2017: 244-250 - [c115]Heinz Riener, Rüdiger Ehlers, Görschwin Fey:
CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. ASP-DAC 2017: 251-256 - [c114]Tino Flenker, Görschwin Fey:
Mapping abstract and concrete hardware models for design understanding. DDECS 2017: 16-21 - [c113]Robert Schmidt, Alberto García Ortiz, Görschwin Fey:
Temporal redundancy latch-based architecture for soft error mitigation. IOLTS 2017: 240-243 - [c112]Tino Flenker, Jan Malburg, Görschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda:
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. ISVLSI 2017: 533-538 - [c111]Heinz Riener, Rüdiger Ehlers, Görschwin Fey:
Counterexample-Guided EF Synthesis of Boolean Functions. MBMV 2017: 67-74 - 2016
- [j17]Jan Malburg, Alexander Finder, Görschwin Fey:
Debugging hardware designs using dynamic dependency graphs. Microprocess. Microsystems 47: 347-359 (2016) - [c110]Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem:
SMT-Based CPS Parameter Synthesis. ARCH@CPSWeek 2016: 126-133 - [c109]Gökçe Aydos, Görschwin Fey:
Exploiting error detection latency for parity-based soft error detection. DDECS 2016: 3-8 - [c108]Niels Thole, Lorena Anghel, Görschwin Fey:
A hybrid algorithm to conservatively check the robustness of circuits. ETS 2016: 1-2 - [c107]Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao:
Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL 2016: 1-8 - [c106]Niels Thole, Heinz Riener, Görschwin Fey:
Equivalence checking on ESL utilizing a priori knowledge. FDL 2016: 1-8 - [c105]Heinz Riener, Görschwin Fey:
Exact diagnosis using boolean satisfiability. ICCAD 2016: 53 - [c104]Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken:
Multilevel design understanding: from specification to logic (invited paper). ICCAD 2016: 133 - [c103]Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey, Jan-Gerd Mess, R. Schmidt:
On the robustness of DCT-based compression algorithms for space applications. IOLTS 2016: 1-2 - [c102]Niels Thole, Görschwin Fey, Alberto García Ortiz:
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. ISVLSI 2016: 278-283 - [c101]Heinz Riener, Görschwin Fey:
Counterexample-guided diagnosis. IVSW 2016: 1-6 - [c100]Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey:
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables. LATS 2016: 14-19 - [c99]Pascal Pieper, Fabian Greif, Görschwin Fey:
Umgebung für automatisierte Tests von Dateisystemen auf NAND-Flash-Speichern. Echtzeit 2016: 127-132 - [c98]Niklas Krafczyk, Heinz Riener, Görschwin Fey:
WCET overapproximation for software in the context of a Cyber-Physical System. VLSI-SoC 2016: 1-6 - 2015
- [j16]Mehdi Dehbashi, Görschwin Fey:
Transaction-based online debug for NoC-based multiprocessor SoCs. Microprocess. Microsystems 39(3): 157-166 (2015) - [c97]Tino Flenker, André Sülflow, Görschwin Fey:
Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation. ATS 2015: 145-150 - [c96]Niels Thole, Heinz Riener, Görschwin Fey:
Equivalence Checking on System Level Using a Priori Knowledge. DDECS 2015: 177-182 - [c95]Gökçe Aydos, Görschwin Fey:
Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture. GI-Jahrestagung 2015: 1415-1429 - [c94]Niels Thole, Görschwin Fey, Alberto García Ortiz:
Conservatively Analyzing Transient Faults. ISVLSI 2015: 50-55 - [c93]Heinz Riener, Michael Kirkedal Thomsen, Görschwin Fey:
Execution Tracing of C Code for Formal Analysis (Extended Abstract). MBMV 2015: 160-164 - [c92]Gökçe Aydos, Görschwin Fey:
Empirical results on parity-based soft error detection with software-based retry. NORCAS 2015: 1-4 - [c91]Gökçe Aydos, Görschwin Fey:
In-circuit Error Detection with Software-based Error Correction - An Alternative to TMR. SyDe Summer School 2015: 272-274 - [c90]Niels Thole, Görschwin Fey:
Formal Verification of Robustness. SyDe Summer School 2015: 305-307 - [c89]Heinz Riener, Rüdiger Ehlers, Görschwin Fey:
Path-Based Program Repair. FESCA 2015: 22-32 - 2014
- [j15]Alexander Finder, André Sülflow, Görschwin Fey:
Latency Analysis for Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 643-647 (2014) - [j14]Jan Malburg, Alexander Finder, Görschwin Fey:
A Simulation-Based Approach for Automated Feature Localization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1886-1899 (2014) - [c88]Jan Malburg, Niklas Krafczyk, Görschwin Fey:
Automatically connecting hardware blocks via light-weight matching techniques. DDECS 2014: 21-26 - [c87]Mehdi Dehbashi, Görschwin Fey:
Sat-based speedpath debugging using waveforms. ETS 2014: 1-6 - [c86]Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler:
MetaSMT: a unified interface to SMT-LIB2. FDL 2014: 1-6 - [c85]Mehdi Dehbashi, Görschwin Fey:
SAT-based speedpath debugging using X traces. IDT 2014: 100-105 - [c84]Niels Thole, Görschwin Fey:
Equivalence Checking on System Level using Stepwise Induction. MBMV 2014: 197-200 - [c83]Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey:
A Logic for Cardinality Constraints (Extended Abstract). MBMV 2014: 217-220 - [c82]Jan Malburg, Emmanuelle Encrenaz-Tiphène, Görschwin Fey:
Mutation Based Feature Localization. MTV 2014: 49-54 - [c81]Mehdi Dehbashi, Görschwin Fey:
Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs. PDP 2014: 400-404 - [c80]Mehdi Dehbashi, Görschwin Fey:
Debug Automation for Synchronization Bugs at RTL. VLSI Design 2014: 44-49 - 2013
- [j13]Mehdi Dehbashi, Görschwin Fey:
Debug Automation for Logic Circuits Under Timing Variations. IEEE Des. Test 30(6): 60-69 (2013) - [j12]Daniel Große, Görschwin Fey, Rolf Drechsler:
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 62 (2013) - [j11]Mehdi Dehbashi, André Sülflow, Görschwin Fey:
Automated design debugging in a testbench-based verification environment. Microprocess. Microsystems 37(2): 206-217 (2013) - [c79]Robert C. Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda:
Reliability analysis reloaded: how will we survive? DATE 2013: 358-367 - [c78]Heinz Riener, Stefan Frehse, Görschwin Fey:
Improving fault tolerance utilizing hardware-software-co-synthesis. DATE 2013: 939-942 - [c77]Jan Malburg, Alexander Finder, Görschwin Fey:
Tuning dynamic data flow analysis to support design understanding. DATE 2013: 1179-1184 - [c76]Mehdi Dehbashi, Görschwin Fey:
Efficient automated speedpath debugging. DDECS 2013: 48-53 - [c75]Alexander Finder, Jan-Philipp Witte, Görschwin Fey:
Debugging HDL designs based on functional equivalences with high-level specifications. DDECS 2013: 60-65 - [c74]Heinz Riener, Görschwin Fey:
Yet a Better Error Explanation Algorithm (Extended Abstract). MBMV 2013: 193-194 - [e1]Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka:
16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-6135-4 [contents] - 2012
- [c73]Mehdi Dehbashi, Görschwin Fey:
Automated Post-Silicon Debugging of Failing Speedpaths. Asian Test Symposium 2012: 13-18 - [c72]Jan Malburg, Alexander Finder, Görschwin Fey:
Automated feature localization for hardware designs using coverage metrics. DAC 2012: 941-946 - [c71]Mehdi Dehbashi, Görschwin Fey:
Automated debugging from pre-silicon to post-silicon. DDECS 2012: 324-329 - [c70]Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
On Modeling and Evaluation of Logic Circuits under Timing Variations. DSD 2012: 431-436 - [c69]Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
Functional analysis of circuits under timing variations. ETS 2012: 1 - [c68]Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler:
Complete and effective robustness checking by means of interpolation. FMCAD 2012: 82-90 - [c67]Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow:
FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference 2012: 260-265 - [c66]Jan Malburg, Alexander Finder, Görschwin Fey:
Automated Feature Localization for Hardware Designs using Coverage Metrics. MBMV 2012: 85-96 - [c65]Heinz Riener, Görschwin Fey:
Model-based diagnosis versus error explanation. MEMOCODE 2012: 43-52 - [c64]Heinz Riener, Görschwin Fey:
FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation. SPIN 2012: 234-240 - [i2]Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda:
Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports 2(8): 57-73 (2012) - 2011
- [j10]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1239-1252 (2011) - [c63]Görschwin Fey:
Orchestrated multi-level information flow analysis to understand SoCs. DAC 2011: 284-285 - [c62]Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler:
Automatic property generation for the formal verification of bus bridges. DDECS 2011: 417-422 - [c61]Mehdi Dehbashi, André Sülflow, Görschwin Fey:
Automated Design Debugging in a Testbench-Based Verification Environment. DSD 2011: 479-486 - [c60]Alexander Finder, André Sülflow, Görschwin Fey:
Latency Analysis for Sequential Circuits. ETS 2011: 129-134 - [c59]Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler:
metaSMT: Focus on Your Application not on Solver Integration. DIFTS@FMCAD 2011 - [c58]Heinz Riener, Roderick Bloem, Görschwin Fey:
Test Case Generation from Mutants Using Model Checking Techniques. ICST Workshops 2011: 388-397 - [c57]Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler:
Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV 2011: 183-192 - [c56]Görschwin Fey:
Assessing System Vulnerability Using Formal Verification Techniques. MEMICS 2011: 47-56 - 2010
- [j9]Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler:
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electron. Test. 26(3): 307-322 (2010) - [j8]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it Inf. Technol. 52(4): 216-223 (2010) - [c55]Rolf Drechsler, Görschwin Fey:
Formal verification meets robustness checking - Techniques and challenges. DDECS 2010: 4 - [c54]Stefan Frehse, Görschwin Fey, Rolf Drechsler:
A better-than-worst-case robustness measure. DDECS 2010: 78-83 - [c53]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
RobuCheck: A Robustness Checker for Digital Circuits. DSD 2010: 226-231 - [c52]Alexander Finder, Görschwin Fey:
Evaluating Debugging Algorithms from a Qualitative Perspective. FDL 2010: 37-42 - [c51]Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler:
Polynomial datapath optimization using constraint solving and formal modelling. ICCAD 2010: 756-761 - [c50]André Sülflow, Görschwin Fey, Rolf Drechsler:
Using QBF to increase accuracy of SAT-based debugging. ISCAS 2010: 641-644 - [c49]Görschwin Fey, André Sülflow, Rolf Drechsler:
Towards Unifying Localization and Explanation for Automated Debugging. MTV 2010: 3-8
2000 – 2009
- 2009
- [b4]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille:
Test Pattern Generation using Boolean Proof Engines. Springer 2009, ISBN 978-90-481-2359-9, pp. I-XII, 1-192 - [j7]Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke:
Advanced verification by automatic property generation. IET Comput. Digit. Tech. 3(4): 338-353 (2009) - [j6]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille:
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. 51(2): 102-111 (2009) - [c48]Görschwin Fey:
Deterministic Algorithms for ATPG under Leakage Constraints. Asian Test Symposium 2009: 313-316 - [c47]Görschwin Fey, André Sülflow, Rolf Drechsler:
Computing bounds for fault tolerance using formal techniques. DAC 2009: 190-195 - [c46]André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler:
Increasing the accuracy of SAT-based debugging. DATE 2009: 1326-1331 - [c45]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
Robustness Check for Multiple Faults Using Formal Techniques. DSD 2009: 85-90 - [c44]Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada:
SAT-based ATPG testing of inter- and intra-gate bridging faults. ECCTD 2009: 643-646 - [c43]André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler:
Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL 2009: 298-303 - [c42]André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler:
Increasing the Accuracy of SAT-based Debugging. MBMV 2009: 47-56 - [c41]André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler:
WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping 2009: 11-17 - 2008
- [b3]Görschwin Fey, Rolf Drechsler:
Robustness and usability in modern design flows. Springer 2008, ISBN 978-1-4020-6535-4, pp. I-XIII, 1-166 - [j5]Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler:
On the construction of small fully testable circuits with low depth. Microprocess. Microsystems 32(5-6): 263-269 (2008) - [j4]Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler:
Automatic Fault Localization for Property Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1138-1149 (2008) - [j3]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1329-1333 (2008) - [c40]Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita:
Targeting Leakage Constraints during ATPG. ATS 2008: 225-230 - [c39]Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke:
Automatic Generation of Complex Properties for Hardware Designs. DATE 2008: 545-548 - [c38]Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler:
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD 2008: 542-549 - [c37]André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler:
Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI 2008: 77-82 - [c36]Görschwin Fey, Rolf Drechsler:
A Basis for Formal Robustness Checking. ISQED 2008: 784-789 - [c35]André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler:
Debugging Design Errors by Using Unsatisfiable Cores. MBMV 2008: 159-168 - [i1]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille:
SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation 2008 - 2007
- [c34]Daniel Tille, Görschwin Fey, Rolf Drechsler:
Instance Generation for SAT-based ATPG. DDECS 2007: 153-156 - [c33]Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler:
On the Construction of Small Fully Testable Circuits with Low Depth. DSD 2007: 563-569 - [c32]Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler:
SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674 - [c31]Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6 - [c30]Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler:
Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV 2007: 81-90 - [c29]