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ORCIDNANOARCH 2015: Boston, MA, USA
- Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2015, Boston, MA, USA, July 8-10, 2015. IEEE Computer Society 2015, ISBN 978-1-4673-7849-9
- Miguel Angel Lastras-Montaño, Amirali Ghofrani, Kwang-Ting Cheng
:
Architecting energy efficient crossbar-based memristive random-access memories. 1-6 - Bi Wu, Yuanqing Cheng, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres, Weisheng Zhao:
An architecture-level cache simulation framework supporting advanced PMA STT-MRAM. 7-12 - Ali Alsuwaiyan, Kartik Mohanram:
MFNW: A Flip-N-Write architecture for multi-level cell non-volatile memories. 13-18 - Colin Pardue, Madhavan Swaminathan, John Bosco Balaguru:
Lossy frequency selective surfaces for gas sensing using ZnO films. 19-20 - Shaloo Rakheja:
Fundamental limits of energy dissipation in spintronic interconnects using optical spin pumping. 21-22 - Yasunao Katayama, Toshiyuki Yamane, Daiju Nakano, Ryosho Nakane, Gouhei Tanaka:
Wave-based device scaling concept for brain-like energy efficiency and integration. 23-24 - Santosh Khasanvis, Mingyu Li, Mostafizur Rahman, Mohammad Salehi Fashami, Ayan Kumar Biswas, Jayasimha Atulasimha, Supriyo Bandyopadhyay, Csaba Andras Moritz:
Physically equivalent magneto-electric nanoarchitecture for probabilistic reasoning. 25-26 - Erya Deng, You Wang, Zhaohao Wang, Jacques-Olivier Klein, Bernard Dieny, Guillaume Prenat, Weisheng Zhao:
Robust magnetic full-adder with voltage sensing 2T/2MTJ cell. 27-32 - Jens Bürger, Alireza Goudarzi, Darko Stefanovic, Christof Teuscher:
Hierarchical composition of memristive networks for real-time computing. 33-38 - Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu:
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery. 39-44 - Winston Haaswijk, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
NEM relay design with biconditional binary decision diagrams. 45-50 - Azam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrián Cristal, Mario Nemirovsky, Osman S. Unsal:
NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs. 51-56 - Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Razvan Nane, Said Hamdioui, Koen Bertels:
Computation-in-memory based parallel adder. 57-62 - Mohsen Imani, Shruti Patil, Tajana Simunic Rosing:
Hierarchical design of robust and low data dependent FinFET based SRAM array. 63-68 - Erik P. DeBenedictis, Jeanine E. Cook, Mark Hoemmen, Tzevetan S. Metodi:
Optimal adiabatic scaling and the processor-in-memory-and-storage architecture (OAS+PIMS). 69-74 - Raqibul Hasan, Chris Yakopcic, Tarek M. Taha:
Ex-situ training of dense memristor crossbar for neuromorphic applications. 75-81 - Onur Tunali, Mustafa Alton:
Defect tolerance in diode, FET, and four-terminal switch based nano-crossbar arrays. 82-87 - Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
Fast march tests for defects in resistive memory. 88-93 - Mohammad Mahmoud A. Taha, Wim J. C. Melis:
Analogue auto-associative memory using a multi-valued memristive memory cell. 94-99 - Peyman Pouyan, Esteve Amat, Antonio Rubio:
Analysis and design of an adaptive proactive reconfiguration approach for memristive crossbar memories. 100-105 - Walt Woods, Mohammad Mahmoud A. Taha, S. J. Dat Tran, Jens Bürger, Christof Teuscher:
Memristor panic - A survey of different device models in crossbar architectures. 106-111 - Pablo Royer, Fernando García-Redondo, Marisa López-Vallejo:
Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm. 112-117 - Aaron Germuth, Alex Aravind:
From kekule cells to molecular switches. 118-123 - Lei Xie, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels:
Interconnect networks for memristor crossbar. 124-129 - Alvaro Velasquez, Sumit Kumar Jha:
Automated synthesis of crossbars for nanoscale computing using formal methods. 130-136 - Patrick Sheridan, Wei D. Lu:
Defect consideratons for robust sparse coding using memristor arrays. 137-138 - Elham Zamanidoost, Michael Klachko, Dmitri B. Strukov, Irina Kataeva:
Low area overhead in-situ training approach for memristor-based classifier. 139-142 - Joseph S. Friedman, Damien Querlioz, Alan V. Sahakian:
Magnetoresistance implications for complementary magnetic tunnel junction logic (CMAT). 143-144 - Zhixi Yang, Jie Han, Fabrizio Lombardi:
Transmission gate-based approximate adders for inexact computing. 145-150 - Ke Chen, Fabrizio Lombardi, Jie Han:
Matrix multiplication by an inexact systolic array. 151-156 - Mostafizur Rahman, Santosh Khasanvis, Jiajun Shi, Mingyu Li, Csaba Andras Moritz:
Architecting 3-D integrated circuit fabric with intrinsic thermal management features. 157-162 - Qi An, Li Su, Jacques-Olivier Klein, Sébastien Le Beux, Ian O'Connor, Weisheng Zhao:
Full-adder circuit design based on all-spin logic device. 163-168 - Jiajun Shi, Mingyu Li, Mostafizur Rahman, Santosh Khasanvis, Csaba Andras Moritz:
Architecting NP-Dynamic Skybridge. 169-174 - Santosh Khasanvis, Mostafizur Rahman, Mingyu Li, Jiajun Shi, Csaba Andras Moritz:
Architecting connectivity for fine-grained 3-D vertically integrated circuits. 175-180 - Christopher H. Bennett, Djaafar Chabi, Theo Cabaret, Bruno Jousselme, Vincent Derycke, Damien Querlioz, Jacques-Olivier Klein:
Supervised learning with organic memristor devices and prospects for neural crossbar arrays. 181-186 - Melika Payvand, Luke Theogarajan:
Exploiting local connectivity of CMOL architecture for highly parallel orientation selective neuromorphic chips. 187-192 - Daniele Garbin, Elisa Vianello, Olivier Bichler, M. Azzaz, Quentin Rafhay, Philippe Candelier, Christian Gamrat, Gérard Ghibaudo, Barbara De Salvo, Luca Perniola:
On the impact of OxRAM-based synapses variability on convolutional neural networks performance. 193-198
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