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ORCIDNANOARCH 2017: Newport, RI, USA
- IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2017, Newport, RI, USA, July 25-26, 2017. IEEE 2017, ISBN 978-1-5090-6037-5
- Linbin Chen, Jie Han, Weiqiang Liu, Fabrizio Lombardi:
Design and operational assessment of an intra-cell hybrid L2 cache. 1-6 - Salin Junsangsri, Fabrizio Lombardi:
AOI-based data-centric circuits for near-memory processing. 7-12 - Mihai Lefter, Thomas Marconi, George Razvan Voicu, Sorin Dan Cotofana
:
Low cost multi-error correction for 3D polyhedral memories. 13-18 - Fuxi Cai, Wei D. Lu:
Epsilon-greedy strategy for online dictionary learning with realistic memristor array constraints. 19-20 - Elena-Ioana Vatajelu, Lorena Anghel:
Fully-connected single-layer STT-MTJ-based spiking neural network under process variability. 21-26 - Ali Alsuwaiyan, Kartik Mohanram:
L3EP: Low latency, low energy program-and-verify for triple-level cell phase change memory. 27-32 - Edouard Giacomin, Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon:
Low-power multiplexer designs using three-independent-gate field effect transistors. 33-38 - Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit:
A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance. 39-44 - Xiaowan Qin, Lang Zeng, Tianqi Gao, Deming Zhang, Mingzhi Long, Youguang Zhang, Weisheng Zhao:
Proposal for novel magnetic memory device with spin momentum locking materials. 45-46 - Zuodong Zhang, Lang Zeng, Tianqi Gao, Deming Zhang, Xiaowan Qin, Mingzhi Long, Youguang Zhang, Haiming Yu, Weisheng Zhao:
Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effect. 47-48 - Guanda Wang, Yue Zhang, Zhizhong Zhang, Jiang Nan, Zhenyi Zheng, Yu Wang, Lang Zeng, Youguang Zhang, Weisheng Zhao:
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction. 49-54 - Alexandre Levisse, Pablo Royer, Bastien Giraud, Jean-Philippe Noël, Mathieu Moreau, Jean-Michel Portal:
Architecture, design and technology guidelines for crosspoint memories. 55-60 - Xuan Hu, Joseph S. Friedman:
Transient model with interchangeability for dual-gate ambipolar CNTFET logic design. 61-66 - Dwaipayan Chakraborty, Sunny Raj, Sumit Kumar Jha:
A compact 8-bit adder design using in-memory memristive computing: Towards solving the Feynman Grand Prize challenge. 67-72 - Jiajun Shi, Mingyu Li, Csaba Andras Moritz:
Power-delivery network in 3D ICs: Monolithic 3D vs. Skybridge 3D CMOS. 73-78 - Mingyu Li, Jiajun Shi, Sachin Bhat, Csaba Andras Moritz:
Fine-grained 3D reconfigurable computing fabric with RRAM. 79-80 - Mohammed Affan Zidan, YeonJoo Jeong, Wei D. Lu:
Hybrid neural network using binary RRAM devices. 81-82 - Sumit Dutta, Saima A. Siddiqui, Felix Buttner, Luqiao Liu, Caroline A. Ross, Marc A. Baldo:
A logic-in-memory design with 3-terminal magnetic tunnel junction function evaluators for convolutional neural networks. 83-88 - Karthik Yogendra, Minsuk Koo, Kaushik Roy:
Energy efficient computation using injection locked bias-field free spin-hall nano-oscillator array with shared heavy metal. 89-94 - Liang Chang, Zhaohao Wang, Youguang Zhang, Weisheng Zhao:
Reconfigurable processing in memory architecture based on spin orbit torque. 95-96 - Zhezhi He, Shaahin Angizi, Farhana Parveen, Deliang Fan:
High performance and energy-efficient in-memory computing architecture based on SOT-MRAM. 97-102 - Walt Woods, Christof Teuscher:
Approximate vector matrix multiplication implementations for neuromorphic applications using memristive crossbars. 103-108 - Sachin Bhat, Sourabh Kulkami, Jiajun Shi, Mingyu Li, Csaba Andras Moritz:
SkyNet: Memristor-based 3D IC for artificial neural networks. 109-114 - S. J. Dat Tran, Christof Teuscher:
Memcapacitive reservoir computing. 115-116 - Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf:
CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices. 117-118 - Arne Heittmann, Tobias G. Noll:
Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells. 119-124 - Christopher H. Bennett, Damien Querlioz, Jacques-Olivier Klein:
Spatio-temporal learning with arrays of analog nanosynapses. 125-130 - Shaloo Rakheja, N. Kani:
Polymorphic spintronic logic gates for hardware security primitives - Device design and performance benchmarking. 131-132 - Kelsey Scharnhorst, Walt Woods, Christof Teuscher, Adam Z. Stieg, James K. Gimzewski:
Non-temporal logic performance of an atomic switch network. 133-138 - Mohammad Mahmoud A. Taha, Christof Teuscher:
Naive Bayesian inference of handwritten digits using a memristive associative memory. 139-140 - Amad Ul Hassen:
Automated synthesis of compact multiplier circuits for in-memory computing using ROBDDs. 141-146 - Sudipta Bhuin, Joseph Sweeney, Samuel Pagliarini, Ayan Kumar Biswas, Lawrence T. Pileggi:
A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ. 147-152 - Wafi Danesh, Mostafizur Rahman:
Linear regression based multi-state logic decomposition approach for efficient hardware implementation. 153-154 - Naveen Kumar Macha, Sandeep Geedipally, Mostafizur Rahman:
Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabric. 155-161 - Nishtha Sharma, Andrew Marshall, Jonathan Bird:
Verilog - A compact model of a ME-MTJ based XNOR/NOR gate. 162-167
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