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ORCIDLawrence T. Pileggi
Larry T. Pileggi – Lawrence T. Pillage
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- affiliation: Carnegie Mellon University, Pittsburgh, USA
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2020 – today
- 2024
[c199]Joseph Sweeney, Deepali Garg, Lawrence T. Pileggi:
Quantifying the Efficacy of Logic Locking Methods. VLSID 2024: 541-546- 2023
- [c198]Shimiao Li
, Ján Drgona, Shrirang Abhyankar, Larry T. Pileggi:
Power Grid Behavioral Patterns and Risks of Generalization in Applied Machine Learning. e-Energy (Companion) 2023: 106-114 - [c197]Brian Singer, Amritanshu Pandey, Shimiao Li, Lujo Bauer, Craig Miller, Lawrence T. Pileggi, Vyas Sekar:
Shedding Light on Inconsistencies in Grid Cybersecurity: Disconnects and Recommendations. SP 2023: 38-55 - [i37]Shimiao Li, Amritanshu Pandey, Larry T. Pileggi:
Contingency Analyses with Warm Starter using Probabilistic Graphical Model. CoRR abs/2304.06727 (2023) - [i36]Shimiao Li, Ján Drgona, Shrirang Abhyankar, Larry T. Pileggi:
Power Grid Behavioral Patterns and Risks of Generalization in Applied Machine Learning. CoRR abs/2304.10702 (2023) - [i35]Aayushya Agarwal, Carmel Fiscko, Soummya Kar, Larry T. Pileggi, Bruno Sinopoli:
An Equivalent Circuit Workflow for Unconstrained Optimization. CoRR abs/2305.14061 (2023) - [i34]Aayushya Agarwal, Larry T. Pileggi:
An Equivalent Circuit Approach to Distributed Optimization. CoRR abs/2305.14607 (2023) - [i33]Carmel Fiscko, Aayushya Agarwal, Yihan Ruan, Soummya Kar, Larry T. Pileggi, Bruno Sinopoli:
Towards Hyperparameter-Agnostic DNN Training via Dynamical System Insights. CoRR abs/2310.13901 (2023) - [i32]Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David M. Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine:
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR abs/2311.02055 (2023) - 2022
- [c196]Larry T. Pileggi, Siyuan Chen, Keshav Harisrikanth, Guanglin Xu, Ken Mai, Franz Franchetti:
A High Throughput Hardware Accelerator for FFTW Codelets: A First Look. HPEC 2022: 1-7 - [i31]Shimiao Li, Amritanshu Pandey, Larry T. Pileggi:
Circuit-theoretic Line Outage Distribution Factor. CoRR abs/2204.07684 (2022) - [i30]Shimiao Li, Amritanshu Pandey, Larry T. Pileggi:
Towards Practical Physics-Informed ML Design and Evaluation for Power Grid. CoRR abs/2205.03673 (2022) - [i29]Aayushya Agarwal, Carmel Fiscko, Soummya Kar, Larry T. Pileggi, Bruno Sinopoli:
ECCO: Equivalent Circuit Controlled Optimization. CoRR abs/2211.08478 (2022) - [i28]Elisaweta Masserova, Deepali Garg, Ken Mai, Lawrence T. Pileggi, Vipul Goyal, Bryan Parno:
Logic Locking - Connecting Theory and Practice. IACR Cryptol. ePrint Arch. 2022: 545 (2022) - 2021
- [j61]Samuel Pagliarini, Joseph Sweeney, Ken Mai, R. D. Shawn Blanton, Larry T. Pileggi, Subhasish Mitra:
Split-Chip Design to Prevent IP Reverse Engineering. IEEE Des. Test 38(4): 109-118 (2021) - [c195]Prashanth Mohan, Oguz Atli, Joseph Sweeney, Onur O. Kibar, Larry T. Pileggi, Ken Mai:
Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion. DATE 2021: 1186-1191 - [c194]Prashanth Mohan, Oguz Atli, Onur O. Kibar, V. Mohammed Zackriya, Larry T. Pileggi, Ken Mai:
Top-down Physical Design of Soft Embedded FPGA Fabrics. FPGA 2021: 1-10 - [c193]Amritanshu Pandey, Aayushya Agarwal, Larry T. Pileggi:
Incremental Model Building Homotopy Approach for Solving Exact AC-Constrained Optimal Power Flow. HICSS 2021: 1-10 - [c192]Priya L. Donti, Aayushya Agarwal, Neeraj Vijay Bedmutha, Larry T. Pileggi, J. Zico Kolter:
Adversarially robust learning for security-constrained optimal power flow. NeurIPS 2021: 28677-28689 - [i27]Joseph Sweeney, Deepali Garg, Lawrence T. Pileggi:
Quantifying the Efficacy of Logic Locking Methods. CoRR abs/2103.06990 (2021) - [i26]Aayushya Agarwal, Amritanshu Pandey, Larry T. Pileggi:
Fast AC Steady-State Power Grid Simulation and Optimization Using Prior Knowledge. CoRR abs/2103.09853 (2021) - [i25]Naeem Turner-Bandele, Amritanshu Pandey, Larry T. Pileggi:
Analytical Inverter-Based Distributed Generator Model for Power Flow Analysis. CoRR abs/2107.04576 (2021) - [i24]Shimiao Li, Amritanshu Pandey, Larry T. Pileggi:
A Convex Method of Generalized State Estimation using Circuit-theoretic Node-breaker Model. CoRR abs/2109.14742 (2021) - [i23]Timothy McNamara, Amritanshu Pandey, Aayushya Agarwal, Larry T. Pileggi:
Two-Stage Homotopy Method to Incorporate Discrete Control Variables into AC-OPF. CoRR abs/2110.07522 (2021) - [i22]Priya L. Donti, Aayushya Agarwal, Neeraj Vijay Bedmutha, Larry T. Pileggi, J. Zico Kolter:
Adversarially Robust Learning for Security-Constrained Optimal Power Flow. CoRR abs/2111.06961 (2021) - [i21]Naeem Turner-Bandele, Amritanshu Pandey, Larry T. Pileggi:
A Risk-Managed Steady-State Analysis to Assess The Impact of Power Grid Uncertainties. CoRR abs/2111.10290 (2021) - [i20]Marko Jereminov, Larry T. Pileggi:
Equivalent Circuit Programming for Power Flow Analysis and Optimization. CoRR abs/2112.01351 (2021) - 2020
- [j60]Joseph Sweeney, Ruben Purdy, Ronald D. Blanton, Lawrence T. Pileggi:
CircuitGraph: A Python package for Boolean circuits. J. Open Source Softw. 5(55): 2646 (2020) - [j59]Mayler G. A. Martins, Samuel N. Pagliarini, Mehmet Meric Isgenc, Lawrence T. Pileggi:
From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 520-532 (2020) - [j58]Samuel N. Pagliarini, Sudipta Bhuin, Mehmet Meric Isgenc, Ayan Kumar Biswas, Lawrence T. Pileggi:
A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks. IEEE Trans. Neural Networks Learn. Syst. 31(4): 1113-1123 (2020) - [j57]Amritanshu Pandey, Larry T. Pileggi:
Steady-State Simulation for Combined Transmission and Distribution Systems. IEEE Trans. Smart Grid 11(2): 1124-1135 (2020) - [j56]Marko Jereminov, David M. Bromberg, Amritanshu Pandey, Martin R. Wagner, Larry T. Pileggi:
Evaluating Feasibility Within Power Flow. IEEE Trans. Smart Grid 11(4): 3522-3534 (2020) - [j55]Mehmet Meric Isgenc, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Lawrence T. Pileggi:
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 585-595 (2020) - [c191]Joseph Sweeney, V. Mohammed Zackriya, Samuel Pagliarini, Lawrence T. Pileggi:
Latch-Based Logic Locking. HOST 2020: 132-141 - [c190]Joseph Sweeney, Marijn J. H. Heule, Lawrence T. Pileggi:
Modeling Techniques for Logic Locking. ICCAD 2020: 80:1-80:9 - [c189]Shimiao Li, Amritanshu Pandey, Soummya Kar, Larry T. Pileggi:
A Circuit-Theoretic Approach to State Estimation. ISGT-Europe 2020: 1126-1130 - [c188]Joseph Sweeney, Marijn Heule, Lawrence T. Pileggi:
Sensitivity Analysis of Locked Circuits. LPAR 2020: 483-497 - [i19]Joseph Sweeney, Samuel Pagliarini, Lawrence T. Pileggi:
Securing Digital Systems via Split-Chip Obfuscation. CoRR abs/2005.10083 (2020) - [i18]Joseph Sweeney, Mohammed Zackriya V, Samuel Pagliarini, Lawrence T. Pileggi:
Latch-Based Logic Locking. CoRR abs/2005.10649 (2020) - [i17]Joseph Sweeney, Marijn J. H. Heule, Lawrence T. Pileggi:
Modeling Techniques for Logic Locking. CoRR abs/2009.10131 (2020) - [i16]Amritanshu Pandey, Aayushya Agarwal, Larry T. Pileggi:
Incremental Model Building Homotopy Approach for Solving Exact AC-Constrained Optimal Power Flow. CoRR abs/2011.00587 (2020) - [i15]Shimiao Li, Amritanshu Pandey, Larry T. Pileggi:
A WLAV-based Robust Hybrid State Estimation using Circuit-theoretic Approach. CoRR abs/2011.06021 (2020) - [i14]Shimiao Li, Amritanshu Pandey, Bryan Hooi, Christos Faloutsos, Larry T. Pileggi:
Dynamic Graph-Based Anomaly Detection in the Electrical Grid. CoRR abs/2012.15006 (2020)
2010 – 2019
- 2019
- [j54]Ioannis Karageorgos, Mehmet Meric Isgenc, Samuel Pagliarini, Lawrence T. Pileggi:
Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography. J. Hardw. Syst. Secur. 3(4): 382-396 (2019) - [c187]Aayushya Agarwal, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi:
Implicitly Modeling Frequency Control within Power Flow. ISGT Europe 2019: 1-5 - [c186]Aleksandar Jovicic, Marko Jereminov, Larry T. Pileggi, Gabriela Hug:
A Linear Formulation for Power System State Estimation including RTU and PMU Measurements. ISGT Europe 2019: 1-5 - [c185]Amritanshu Pandey, Aayushya Agarwal, Marko Jereminov, Martin R. Wagner, David M. Bromberg, Larry T. Pileggi:
Robust Sequential Steady-State Analysis of Cascading Outages. ISGT Europe 2019: 1-5 - [c184]Fazle Sadi, Joe Sweeney, Tze Meng Low, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
Efficient SpMV Operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization. MICRO 2019: 347-358 - [i13]Marko Jereminov, Bryan Hooi, Amritanshu Pandey, Hyun Ah Song, Christos Faloutsos, Lawrence T. Pileggi:
Impact of Load Models on Power Flow Optimization. CoRR abs/1902.04154 (2019) - [i12]Amritanshu Pandey, Larry T. Pileggi:
Steady-State Simulation for Combined Transmission and Distribution Systems. CoRR abs/1907.12725 (2019) - [i11]Aayushya Agarwal, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi:
Implicitly Modeling Frequency Control within Power Flow. CoRR abs/1908.11778 (2019) - [i10]Amritanshu Pandey, Aayushya Agarwal, Marko Jereminov, Larry T. Pileggi:
Robust Online Simulation Framework for Grid Restoration Under Loss of SCADA. CoRR abs/1910.03557 (2019) - [i9]Shimiao Li, Amritanshu Pandey, Aayushya Agarwal, Marko Jereminov, Larry T. Pileggi:
A LASSO-Inspired Approach for Localizing Power System Infeasibility. CoRR abs/1911.05154 (2019) - [i8]Shimiao Li, Amritanshu Pandey, Soummya Kar, Larry T. Pileggi:
A Circuit-Theoretic Approach to State Estimation. CoRR abs/1911.05155 (2019) - 2018
- [j53]Shaolong Liu, Taimur Gibran Rabuske, Jeyanandh Paramesh, Lawrence T. Pileggi, Jorge R. Fernandes:
Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(2): 458-470 (2018) - [j52]Samuel N. Pagliarini, Mehmet Meric Isgenc, Mayler G. A. Martins, Lawrence T. Pileggi:
Application and Product-Volume-Specific Customization of BEOL Metal Pitch. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1627-1636 (2018) - [c183]Bryan Hooi, Leman Akoglu, Dhivya Eswaran, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi, Christos Faloutsos:
ChangeDAR: Online Localized Change Detection for Sensor Data on a Graph. CIKM 2018: 507-516 - [c182]Shaolong Liu, Jeyanandh Paramesh, Larry T. Pileggi, Taimur Gibran Rabuske, Jorge Fernandcs:
A 125 MS/s 10.4 ENOB 10.1 fJ/Conv-Step Multi-Comparator SAR ADC with Comparator Noise Scaling in 65nm CMOS. ESSCIRC 2018: 22-25 - [c181]Fazle Sadi, Joe Sweeney, Scott McMillan, Tze Meng Low, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV. HPEC 2018: 1-7 - [c180]Thomas C. Jackson, Samuel Pagliarini, Lawrence T. Pileggi:
An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS. ICRC 2018: 1-7 - [c179]Bryan Hooi, Dhivya Eswaran, Hyun Ah Song, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi, Christos Faloutsos:
GridWatch: Sensor Placement and Anomaly Detection in the Electrical Grid. ECML/PKDD (1) 2018: 71-86 - [c178]Bryan Hooi, Hyun Ah Song, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi, Christos Faloutsos:
StreamCast: Fast and Online Mining of Power Grid Time Sequences. SDM 2018: 531-539 - [i7]Amritanshu Pandey, Marko Jereminov, Martin R. Wagner, David M. Bromberg, Gabriela Hug, Larry T. Pileggi:
Robust Steady State Analysis of the Power Grid. CoRR abs/1803.01211 (2018) - [i6]Martin R. Wagner, Amritanshu Pandey, Marko Jereminov, Larry T. Pileggi:
Robust Probabilistic Analysis of Transmission Power Systems based on Equivalent Circuit Formulation. CoRR abs/1804.07794 (2018) - 2017
- [c177]Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young:
A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. DAC 2017: 18:1-18:2 - [c176]Fazle Sadi, Larry T. Pileggi, Franz Franchetti:
Algorithm and hardware co-optimized solution for large SpMV problems. HPEC 2017: 1-7 - [c175]Marko Jereminov, Amritanshu Pandey, Hyun Ah Song, Bryan Hooi, Christos Faloutsos, Larry T. Pileggi:
Linear load model for robust power system analysis. ISGT Europe 2017: 1-6 - [c174]Samuel Pagliarini, Mayler G. A. Martins, Lawrence T. Pileggi:
Virtual characterization for exhaustive DFM evaluation of logic cell libraries. ISQED 2017: 93-98 - [c173]Mehmet Meric Isgenc, Samuel Pagliarini, Renzhi Liu, Larry T. Pileggi:
Evaluating the benefits of relaxed BEOL pitch for deeply scaled ICs. ISQED 2017: 180-185 - [c172]Sudipta Bhuin, Joseph Sweeney, Samuel Pagliarini, Ayan Kumar Biswas, Lawrence T. Pileggi:
A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ. NANOARCH 2017: 147-152 - [c171]Hyun Ah Song, Bryan Hooi, Marko Jereminov, Amritanshu Pandey, Larry T. Pileggi, Christos Faloutsos:
PowerCast: Mining and Forecasting Power Grid Sequences. ECML/PKDD (2) 2017: 606-621 - [i5]Amritanshu Pandey, Marko Jereminov, Martin R. Wagner, Gabriela Hug, Larry T. Pileggi:
Robust Convergence of Power Flow using Tx Stepping Method with Equivalent Circuit Formulation. CoRR abs/1711.01471 (2017) - [i4]Amritanshu Pandey, Marko Jereminov, Gabriela Hug, Larry T. Pileggi:
Improving Power Flow Robustness via Circuit Simulation Methods. CoRR abs/1711.01624 (2017) - [i3]Amritanshu Pandey, Marko Jereminov, Xin Li, Gabriela Hug, Larry T. Pileggi:
Aggregated Load and Generation Equivalent Circuit Models with Semi-Empirical Data Fitting. CoRR abs/1711.06907 (2017) - 2016
- [j51]Renzhi Liu, Lawrence T. Pileggi, Jeffrey A. Weldon:
A wideband RF receiver with extended statistical element selection based harmonic rejection calibration. Integr. 52: 185-194 (2016) - [c170]Fa Wang, Shihui Yin, Minhee Jun, Xin Li, Tamal Mukherjee, Rohit Negi, Larry T. Pileggi:
Re-thinking polynomial optimization: Efficient programming of reconfigurable radio frequency (RF) systems by convexification. ASP-DAC 2016: 545-550 - [c169]Renzhi Liu, Jeffrey A. Weldon, Larry T. Pileggi:
Extended statistical element selection: a calibration method for high resolution in analog/RF designs. DAC 2016: 104:1-104:6 - [c168]Fazle Sadi, Larry T. Pileggi, Franz Franchetti:
3D DRAM based application specific hardware accelerator for SpMV. HPEC 2016: 1 - [c167]Rongye Shi, Thomas C. Jackson, Brian Swenson, Soummya Kar, Lawrence T. Pileggi:
On the design of phase locked loop oscillatory neural networks: Mitigation of transmission delay effects. IJCNN 2016: 2039-2046 - [c166]Amritanshu Pandey, Marko Jereminov, Xin Li, Gabriela Hug, Larry T. Pileggi:
Unified power system analyses and models using equivalent circuit formulation. ISGT 2016: 1-5 - [c165]Marko Jereminov, Amritanshu Pandey, David M. Bromberg, Xin Li, Gabriela Hug, Larry T. Pileggi:
Steady-state analysis of power system harmonics using equivalent split-circuit models. ISGT Europe 2016: 1-6 - [c164]L. Richard Carley, Gurkan Colak, Louis Chomas, Larry T. Pileggi, Kenneth Mai:
Technologies for secure RFID authentication of medicinal pills and capsules. RFID-TA 2016: 10-15 - 2015
- [j50]Mohamed M. Sabry, Mingyu Gao, Gage Hills, Chi-Shuen Lee, Greg Pitner, Max M. Shulaker, Tony F. Wu, Mehdi Asheghi, Jeffrey Bokor, Franz Franchetti, Kenneth E. Goodson, Christos Kozyrakis, Igor L. Markov, Kunle Olukotun, Larry T. Pileggi, Eric Pop, Jan M. Rabaey, Christopher Ré, H.-S. Philip Wong, Subhasish Mitra:
Energy-Efficient Abundant-Data Computing: The N3XT 1, 000x. Computer 48(12): 24-33 (2015) - [j49]Vehbi Calayir, Larry T. Pileggi:
Device Requirements and Technology-Driven Architecture Optimization for Analog Neurocomputing. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 162-172 (2015) - [j48]Thomas C. Jackson, Abhishek A. Sharma, James A. Bain, Jeffrey A. Weldon, Lawrence T. Pileggi:
Oscillatory Neural Networks Based on TMO Nano-Oscillators and Multi-Level RRAM Cells. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(2): 230-241 (2015) - [j47]Renzhi Liu, Larry T. Pileggi:
Low-Overhead Self-Healing Methodology for Current Matching in Current-Steering DAC. IEEE Trans. Circuits Syst. II Express Briefs 62-II(7): 651-655 (2015) - [c163]Ying-Chih Wang, Shihui Yin, Minhee Jun, Xin Li, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi:
Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement data. ASP-DAC 2015: 441-446 - [c162]Huseyin Ekin Sumbul, Kaushik Vaidyanathan, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi:
A synthesis methodology for application-specific logic-in-memory designs. DAC 2015: 196:1-196:6 - [c161]Vehbi Calayir, Mohamed Darwish, Jeffrey A. Weldon, Larry T. Pileggi:
Analog neuromorphic computing enabled by multi-gate programmable resistive devices. DATE 2015: 928-931 - [c160]Thomas C. Jackson, Abhishek A. Sharma, James A. Bain, Jeffrey A. Weldon, Lawrence T. Pileggi:
An RRAM-based Oscillatory Neural Network. LASCAS 2015: 1-4 - [c159]Qi Guo, Tze Meng Low, Nikolaos Alachiotis, Berkin Akin, Larry T. Pileggi, James C. Hoe, Franz Franchetti:
Enabling portable energy efficiency with memory accelerated library. MICRO 2015: 750-761 - 2014
- [j46]Vanessa Hung-Chu Chen, Lawrence T. Pileggi:
A 69.5 mW 20 GS/s 6b Time-Interleaved ADC With Embedded Time-to-Digital Calibration in 32 nm CMOS SOI. IEEE J. Solid State Circuits 49(12): 2891-2901 (2014) - [j45]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman:
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2243-2252 (2014) - [c158]Jun Tao, Ying-Chih Wang, Minhee Jun, Xin Li, Rohit Negi, Tamal Mukherjee, Lawrence T. Pileggi:
Toward efficient programming of reconfigurable radio frequency (RF) receivers. ASP-DAC 2014: 256-261 - [c157]Renzhi Liu, Larry T. Pileggi, Jeffrey A. Weldon:
A wideband RF receiver with >80 dB harmonic rejection ratio. CICC 2014: 1-4 - [c156]Kaushik Vaidyanathan, Bishnu Prasad Das, Larry T. Pileggi:
Detecting Reliability Attacks during Split Fabrication using Test-only BEOL Stack. DAC 2014: 156:1-156:6 - [c155]Minhee Jun, Rohit Negi, Ying-Chih Wang, Tamal Mukherjee, Xin Li, Jun Tao, Larry T. Pileggi:
Joint invariant estimation of RF impairments for reconfigurable Radio Frequency(RF) front-end. GLOBECOM Workshops 2014: 954-959 - [c154]Kaushik Vaidyanathan, Bishnu Prasad Das, Huseyin Ekin Sumbul, Renzhi Liu, Larry T. Pileggi:
Building trusted ICs using split fabrication. HOST 2014: 1-6 - [c153]Kaushik Vaidyanathan, Renzhi Liu, Huseyin Ekin Sumbul, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi:
Efficient and secure intellectual property (IP) design with split fabrication. HOST 2014: 13-18 - [c152]Fazle Sadi, Berkin Akin, Doru-Thom Popovici, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory. HPEC 2014: 1-6 - [c151]Kaushik Vaidyanathan, Lars Liebmann, Andrzej J. Strojwas, Larry T. Pileggi:
Sub-20 nm design technology co-optimization for standard cell logic. ICCAD 2014: 124-131 - [c150]Vanessa Hung-Chu Chen, Lawrence T. Pileggi:
22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI. ISSCC 2014: 380-381 - [c149]Minhee Jun, Rohit Negi, Jun Tao, Ying-Chih Wang, Shihui Yin, Tamal Mukherjee, Xin Li, Lawrence T. Pileggi:
Environment-Adaptable Efficient Optimization for Programming of Reconfigurable Radio Frequency (RF) Receivers. MILCOM 2014: 1459-1465 - 2013
- [j44]Matthias Althoff, Akshay Rajhans, Bruce H. Krogh, Soner Yaldiz, Xin Li, Larry T. Pileggi:
Formal verification of phase-locked loops using reachability analysis and continuization. Commun. ACM 56(10): 97-104 (2013) - [j43]Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman:
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits 48(5): 1138-1150 (2013) - [j42]Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman:
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits 48(6): 1539 (2013) - [j41]Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman:
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2009-2017 (2013) - [j40]Qiuling Zhu, Christian R. Berger, Eric L. Turner, Larry T. Pileggi, Franz Franchetti:
Local Interpolation-based Polar Format SAR: Algorithm, Hardware Implementation and Design Automation. J. Signal Process. Syst. 71(3): 297-312 (2013) - [c148]Qiuling Zhu, Berkin Akin, Huseyin Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. 3DIC 2013: 1-7 - [c147]Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman:
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. CICC 2013: 1-4 - [c146]Qiuling Zhu, Tobias Graf, Huseyin Ekin Sumbul, Larry T. Pileggi, Franz Franchetti:
Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware. HPEC 2013: 1-6 - [c145]Vehbi Calayir, Tom Jackson, Augusto Tazzoli, Gianluca Piazza, Larry T. Pileggi:
Neurocomputing and associative memories based on ovenized aluminum nitride resonators. IJCNN 2013: 1-8 - [c144]