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ORCIDReCoSoC 2012: York, United Kingdom
- Leandro Soares Indrusiak, Guy Gogniat, Nikolaos S. Voros:
7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), York, United Kingdom, July 9-11, 2012. IEEE 2012, ISBN 978-1-4673-2570-7 - Gary Plumbridge, Neil C. Audsley:
Translating Java for resource constrained embedded systems. 1-8 - Anastasiia Butko, Rafael Garibotti
, Luciano Ost, Gilles Sassatelli:
Accuracy evaluation of GEM5 simulator system. 1-7 - Sébastien Guillet, Florent de Lamotte, Nicolas Le Griguer, Éric Rutten, Guy Gogniat, Jean-Philippe Diguet:
Designing formal reconfiguration control using UML/MARTE. 1-8 - Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
Distributed control for reconfigurable FPGA systems: A high-level design approach. 1-8 - Diana Göhringer, Mounir Chemaou, Michael Hübner:
Invited paper: On-chip monitoring for adaptive heterogeneous multicore systems. 1-7 - Catalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Gaydadjiev:
On implementability of Polymorphic Register Files. 1-6 - Kyprianos Papadimitriou, Charalampos Vatsolakis, Dionisios N. Pnevmatikatos:
Invited paper: Acceleration of computationally-intensive kernels in the reconfigurable era. 1-5 - João M. P. Cardoso:
Programming strategies for runtime adaptability. 1-8 - Dominic Hillenbrand, Christian Brugger, Jie Tao, Shufan Yang, Matthias Norbert Balzer:
RIVER architecture: Reconfigurable flow and fabric for parallel stream processing on FPGAs. 1-8 - Fábio P. Itturriet, Gabriel L. Nazar, Ronaldo Rodrigues Ferreira, Álvaro F. Moreira, Luigi Carro:
Adaptive parallelism exploitation under physical and real-time constraints for resilient systems. 1-8 - Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano:
Dynamically reconfigurable flux limiter functions in MUSCL scheme. 1-7 - Timo Stripf, Oliver Oey, Thomas Bruckschlögl, Ralf König, Michael Hübner, Jürgen Becker, Gerard K. Rauwerda, Kim Sunesen, Nikolaos Kavvadias, Grigoris Dimitroulakos, Kostas Masselos, Dimitrios Kritharidis, Nikolaos Mitas, George Goulas, Panayiotis Alefragis, Nikolaos S. Voros, Steven Derrien, Daniel Ménard, Olivier Sentieys, Diana Göhringer, Thomas Perschke:
A flexible approach for compiling scilab to reconfigurable multi-core embedded systems. 1-8 - Etienne Brosse, Imran Rafiq Quadri, Andrey Sadovykh, Frank Ieromnimon, Dimitrios Kritharidis, Rafael Catrou, Michel Sarlotte:
ENOSYS FP7 EU project: An integrated modeling and synthesis flow for embedded systems design. 1-5 - Marco D. Santambrogio, Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Christian Pilato, Georgi Gaydadjiev, Dirk Stroobandt, Tom Davidson, Tobias Becker, Tim Todman, Wayne Luk, Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Donatella Sciuto:
Smart technologies for effective reconfiguration: The FASTER approach. 1-7 - Imran Rafiq Quadri, Etienne Brosse, Ian Gray, Nikolas Drivalos Matragkas, Leandro Soares Indrusiak, Matteo Rossi, Alessandra Bagnato, Andrey Sadovykh:
MADES FP7 EU project: Effective high level SysML/MARTE methodology for real-time and embedded avionics systems. 1-8 - Gianluca Durelli, Christian Pilato, Andrea Cazzaniga, Donatella Sciuto, Marco D. Santambrogio:
Automatic run-time manager generation for reconfigurable MPSoC architectures. 1-8 - Pamela Wattebled, Jean-Philippe Diguet, Jean-Luc Dekeyser:
Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems. 1-8 - Patrick Bellasi, Giuseppe Massari, William Fornaciari:
A RTRM proposal for multi/many-core platforms and reconfigurable applications. 1-8 - François Philipp, Conrad Klytta, Manfred Glesner, Élvio Dutra:
Hardware acceleration of combined cipher and forward error correction for low-power wireless applications. 1-7 - Miao He, Yanzhe Cui, Mohammad H. Mahoor, Richard M. Voyles:
A heterogeneous modules interconnection architecture for FPGA-based partial dynamic reconfiguration. 1-7 - Miguel Lombardo, Julio Camarero, Juan Valverde, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Power management techniques in an FPGA-based WSN node for high performance applications. 1-8 - Siew Kei Lam, Thambipillai Srikanthan, Christopher T. Clarke:
Exploiting FPGA-aware merging of custom instructions for runtime reconfiguration. 1-8 - Dimitris Bekiaris, Efstathios Sotiriou-Xanthopoulos, George Economakos, Dimitrios Soudris:
Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments. 1-8 - Renaud Van Langendonck, Angelo Kuti Lusala, Jean-Didier Legat:
MPSoCDK: A framework for prototyping and validating MPSoC projects on FPGAs. 1-8 - Daniela Genius, Khouloud Zine el Abidine:
A solution to the data re-ordering problem for multi-pipeline streaming applications on clustered MPSoC. 1-8 - Adrian Racu, Leandro Soares Indrusiak:
Using genetic algorithms to map hard real-time on NoC-based systems. 1-8 - Anup Das, Akash Kumar, Bharadwaj Veeravalli:
Fault-tolerant network interface for spatial division multiplexing based Network-on-Chip. 1-8 - Mohammad Fattah, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila:
Transport layer aware design of network interface in many-core systems. 1-7 - Pascal Cotret, Florian Devic, Guy Gogniat, Benoît Badrignans, Lionel Torres:
Security enhancements for FPGA-based MPSoCs: A boot-to-runtime protection flow for an embedded Linux-based system. 1-8 - Haoyuan Ying, Thomas Hollstein, Klaus Hofmann:
Communication-centric high level synthesis metrics for low vertical channel density 3-dimensional Networks-on-Chip. 1-6 - Leandro Soares Indrusiak, Imran Rafiq Quadri, Ian Gray, Neil C. Audsley, Andrey Sadovykh:
A MARTE subset to enable application-platform co-simulation and schedulability analysis of NoC-based embedded systems. 1-7 - Mark Milward, David Stevens, Vassilios A. Chouliaras:
Embedded UML design flow to the configurable LE1 MultiCore VLIW processor. 1-8 - Waqar Hussain, Tapani Ahonen, Roberto Airoldi, Jari Nurmi:
Energy and power estimation of Coarse-Grain Reconfigurable Array based Fast Fourier Transform accelerators. 1-4 - Mohsin Amin, Mihkel Tagel, Gert Jervan, Thomas Hollstein:
Design methodology for fault-tolerant heterogeneous MPSoC under real-time constraints. 1-6 - Clément Foucher, Fabrice Muller, Alain Giulieri:
Fast integration of hardware accelerators for dynamically reconfigurable architecture. 1-7 - Daniel Llamocca, Marios S. Pattichis, Cesar Carranza:
A framework for self-reconfigurable DCTs based on multiobjective optimization of the Power-Performance-Accuracy space. 1-6 - Ross A. Elliot, Martin A. Enderwitz, Ke He, Faisal Darbari, Louise Crockett, Stephan Weiss, Robert W. Stewart:
Partially reconfigurable TVWS transceiver for use in UK and US markets. 1-6 - Nicolas Serna, François Verdier:
High-level model of sensor architecture for hardware and software design space exploration. 1-8 - Taras Iakymchuk, Alfredo Rosado, José V. Francés, Manuel Bataller:
Fast spiking neural network architecture for low-cost FPGA devices. 1-6 - André L. S. Braga, Janier Arias-Garcia, Carlos H. Llanos, Márcio Dorn, Alfredo Foltran, Leandro dos Santos Coelho:
Hardware implementation of GMDH-type artificial neural networks and its use to predict approximate three-dimensional structures of proteins. 1-8 - Masoud Daneshtalab, Masoumeh Ebrahimi, Juha Plosila:
GLB - Efficient Global Load Balancing method for moderating congestion in on-chip networks. 1-5
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