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ORCIDSBCCI 2014: Aracaju, Brazil
- Edward David Moreno Ordonez, Rodolfo Jardim de Azevedo, Peter R. Kinget:
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, Aracaju, Brazil, September 1-5, 2014. ACM 2014, ISBN 978-1-4503-3156-2 - Andre Aziz, Maria Cireno, Edna Barros
, Bruno O. Prado:
Balanced Prefetching Aggressiveness Controller for NoC-based Multiprocessor. 1:1-1:7 - Crystal de Menezes Santos, Abel G. Silva-Filho:
Bee Colony Algorithm Applied to Memory Architecture Exploration intended for Energy Reduction. 2:1-2:7 - Gabriel R. Guerreiro, João Navarro:
Design for Stability of Active Inductor with Feedback Resistance. 3:1-3:6 - Wilson J. Bortoletto Machado, Calvin Plett:
Impact of ESD Protection and Power Supply Decoupling on 10 GHz Low Noise Amplifier. 4:1-4:7 - Giuseppe Roa, Tugdual Le Pelleter, Agnès Bonvilain, Alejandro Chagoya, Laurent Fesquet:
Designing ultra-low power systems with non-uniform sampling and event-driven logic. 5:1-5:6 - Moacir Fernandes Cortinhas Monteiro, Hamilton Klimach, Sergio Bampi:
High Linearity and Large Output Swing Sub-Hz Pre-amplifier for Portable Biomedical Applications. 7:1-7:7 - Carlos Augusto de Moraes Cruz, Carlos A. dos Reis Filho, Davies William de Lima Monteiro:
Improved Charge Pump Circuits for Standard CMOS Technologies. 8:1-8:5 - Raphael Andreoni Camponogara Viera, César Augusto Prior, Jorge V. de la Cruz, João Baptista dos Santos Martins:
System-Level Design of a Reconfigurable CT SD Modulator for Multi-Standard Wireless Applications. 9:1-9:6 - Rafael Kioji Vivas Maeda, Frank Sill Torres:
CLEVER: Cross-Layer Error Verification, Evaluation and Reporting. 10:1-10:7 - Shuo Yang, Robert Wille, Rolf Drechsler:
Determining Cases of Scenarios to Improve Coverage in Simulation-based Verification. 11:1-11:7 - Viviane Lucy Santos de Souza, Abel G. Silva-Filho:
MogaMap and DynPack: Multi-Objective Mapping and Packing Algorithms for Optimization of Area, Performance and Power Consumption in FPGAs. 12:1-12:6 - Jannis Stoppe, Robert Wille, Rolf Drechsler:
Validating SystemC Implementations Against Their Formal Specifications. 13:1-13:8 - Ariane Alves Almeida, Carlos H. Llanos, Janier Arias-Garcia, Mauricio Ayala-Rincón:
Verification of Hardware Implementations through Correctness of their Recursive Definitions in PVS. 14:1-14:8 - Rolf Drechsler, Hoang Minh Le, Mathias Soeken:
Self-Verification as the Key Technology for Next Generation Electronic Systems. 15:1-15:4 - Matheus Trevisan, Michel Evandro Arendt, Adriel Ziesemer, Ricardo Augusto da Luz Reis, Ney Laert Vilar Calazans:
Automated Synthesis of Cell Libraries for Asynchronous Circuits. 16:1-16:7 - Alisson J. C. Lanot, Tiago R. Balen:
Reliability Analysis of a 130nm Charge Redistribution SAR ADC under Single Event Effects. 17:1-17:7 - Eduardo Wächter, Augusto Erichsen, Leonardo Juracy, Alexandre M. Amory, Fernando Gehm Moraes:
A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance Constrained Applications. 18:1-18:7 - Solon J. Spiegel:
An Overview of Radio Frequency Technologies and Their Influence on the Power Efficiency of Wireless Communication Systems. 19:1-19:7 - Jader A. De Lima:
A Compact and Power-Efficient CMOS Battery Charger for Implantable Devices. 20:1-20:6 - David Cordova, Pedro Toledo, Eric E. Fabris:
A Low-Voltage Current Reference with High Immunity to EMI. 21:1-21:6 - Pedro Toledo, Hamilton Klimach, David Cordova, Sergio Bampi, Eric E. Fabris:
Self-biased CMOS Current Reference based on the ZTC Operation Condition. 22:1-22:7 - Oscar E. Mattia, Hamilton Klimach, Sergio Bampi:
Sub-1 V Supply Nano-Watt MOSFET-Only Threshold Voltage Extractor Circuit. 23:1-23:6 - Jean-Philippe Diguet:
Self-Adaptive Network On Chips. 24:1-24:6 - Marcio Bender Machado, Mohamad Sawan, Márcio Cherem Schneider, Carlos Galup-Montoro:
10 mV: 1V Step-up Converter for Energy Harvesting Applications. 25:1-25:5 - Alfredo Olmos, Juan Pablo Martinez Brito, Fabrício Jorge Antunes Ferreira, Fernando Chávez, Marcelo Soares Lubaszewski:
A 2-Transistor Sub-1V Low Power Temperature Compensated CMOS Voltage Reference. 26:1-26:5 - David Cordova, Sergio Bampi, Eric E. Fabris:
A CMOS Down-Conversion Mixer with High IIP2 and IIP3 for Multi-Band and Multiple Standards. 27:1-27:7 - André F. Ponchet, Ezio M. Bastida, Roberto R. Panepucci, Stefan Tenenbaum, Jacobus W. Swart:
SiGe HBT mm-Wave DC Coupled Ultra-wide-band Low Noise Monolithic Amplifiers. 28:1-28:7 - Elverton C. Fazzion, Osvaldo L. H. M. Fonseca, José Augusto Miranda Nacif, Omar P. Vilela Neto, Antônio Otávio Fernandes, Douglas S. Silva:
A Quantum-Dot Cellular Automata Processor Design. 29:1-29:7 - Felipe P. da Silva, Alan Oliveira de Sá, Nadia Nedjah, Luiza de Macedo Mourelle:
An Efficient Parallel Yet Pipelined Reconfigurable Architecture for M-PLN Weightless Neural Networks. 30:1-30:7 - Lívia Amaral, Dieison Silveira, Guilherme Povala, Luciano Volcan Agostini, Marcelo Schiavon Porto, Bruno Zatt:
A Memory Energy Consumption Analysis of Motion Estimation Algorithms using Data Reuse in Video Coding Systems. 31:1-31:6 - Massimo Alioto, David Esseni:
Performance and Impact of Process Variations in Tunnel-FET Ultra-Low Voltage Digital Circuits. 32:1-32:6 - Luciano Loder, Adão Antônio de Souza Jr., Marcelo Schiavon Fay, Rafael Soares:
Towards a Framework to Perform DPA Attack on GALS Pipeline Architectures. 33:1-33:7 - Gustavo Sanchez, Bruno Zatt, Marcelo Schiavon Porto, Luciano Volcan Agostini:
A Real-Time 5-Views HD 1080p Architecture for 3D-HEVC Depth Modeling Mode 4. 34:1-34:6 - Jens Spinner, Jürgen Freudenberger:
Design and Implementation of a Pipelined Decoder for Generalized Concatenated Codes Format. 35:1-35:6 - Luiz Henrique Cancellier, André Beims Bräscher, Ismael Seidel, José Luís Güntzel:
Energy-Efficient Hadamard-Based SATD Architectures. 36:1-36:6 - Tiago S. Curtinhas, Duarte Lopes de Oliveira, Lester de Abreu Faria, Osamu Saotome:
A novel State Assignment method for Extended Burst-Mode FSM design using Genetic Algorithm. 39:1-39:7 - Jody Maick Matos, Marcus Ritt, Renato P. Ribas, André Inácio Reis:
Deriving Reduced Transistor Count Circuits from AIGs. 40:1-40:7 - Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Jr.:
Exploring Independent Gates in FinFET-Based Transistor Network Generation. 41:1-41:6 - Michael Kärgel, Markus Olbrich, Erich Barke:
Simulation Based Verification with Range Based Signal Representations for Mixed-Signal Systems. 42:1-42:7 - Marcelo Ruaro, Everton Alceu Carara, Fernando Gehm Moraes:
Runtime QoS Support for MPSoC: a Processor Centric Approach. 43:1-43:7 - Carlos Moratelli, Samir Zampiva, Fabiano Hessel:
Full-Virtualization on MIPS-based MPSOCs embedded platforms with real-time support. 44:1-44:7 - Stephanie Friederich, Jan Heisswolf, Jürgen Becker:
Hardware/software debugging of large scale many-core architectures. 45:1-45:7 - Alexsandro Cristovão Bonatto, Marcelo Negreiros, Fábio I. Pereira, André Borin Soares, Altamiro Amadeu Susin:
Adaptive Shared Memory Control for Multimedia Systems-on-Chip. 46:1-46:7
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