default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID19. SCOPES 2016: St. Goar, Germany
- Sander Stuijk:
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2016, Sankt Goar, Germany, May 23-25, 2016. ACM 2016, ISBN 978-1-4503-4320-6
Keynotes
- Marco Bekooij:
From dataflow analysis basics to the programming of ASICs. 1 - Muhammad Shafique
, Semeen Rehman, Florian Kriebel, Jörg Henkel:
Cross-Layer Reliability Modeling and Optimization: Compiler and Run-Time System Interactions. 2-5
Full Papers
- Christakis Lezos, Ioannis Latifis, Grigoris Dimitroulakos, Konstantinos Masselos:
Compiler-Directed Data Locality Optimization in MATLAB. 6-9 - Jan van Lunteren:
Scalable DFA Compilation for High-Performance Regular-Expression Matching. 10-19 - Shuoxin Lin, Yanzhou Liu, William Plishker, Shuvra S. Bhattacharyya:
A Design Framework for Mapping Vectorized Synchronous Dataflow Graphs onto CPU-GPU Platforms. 20-29 - Peter Koek, Stefan J. Geuns, Joost P. H. M. Hausmans, Henk Corporaal, Marco Jan Gerrit Bekooij:
CSDFa: A Model for Exploiting the Trade-Off between Data and Pipeline Parallelism. 30-39 - Ulysse Beaugnon, Albert Cohen, Marc Pouzet:
In-Place Update in a Dataflow Synchronous Language: A Retiming-Enabled Language Experiment. 40-49 - Omair Rafique, Klaus Schneider:
Introducing MoC Drivers for the Integration of Sensor-Actuator Behaviors in Model-Based Design Flows of Embedded Systems. 50-59 - Philip S. Kurtin, Joost P. H. M. Hausmans, Marco Jan Gerrit Bekooij:
HAPI: An Event-Driven Simulator for Real-Time Multiprocessor Systems. 60-66 - Richard Plangger, Andreas Krall:
Vectorization in PyPy's Tracing Just-In-Time Compiler. 67-76 - Arno Luppold, Christina Kittsteiner, Heiko Falk:
Cache-Aware Instruction SPM Allocation for Hard Real-Time Systems. 77-85 - Dominic Oehlert, Arno Luppold, Heiko Falk:
Practical Challenges of ILP-based SPM Allocation Optimizations. 86-89 - Wouter van Teijlingen, Rene van Leuken, Carlo Galuzzi, Bart Kienhuis:
Determining Performance Boundaries on High-Level System Specifications. 90-97 - Guus Kuiper, Stefan J. Geuns, Joost P. H. M. Hausmans, Marco Jan Gerrit Bekooij:
Compositional Temporal Analysis Method for Fixed Priority Pre-emptive Scheduled Modal Stream Processing Applications. 98-107 - Tim Schmidt, Guantao Liu, Rainer Dömer:
Automatic Generation of Thread Communication Graphs from SystemC Source Code. 108-115 - Erwan Jahier:
RDBG: a Reactive Programs Extensible Debugger. 116-125 - Nicolas Melot, Christoph W. Kessler, Jörg Keller:
Energy-Optimized Static Scheduling for Many-Cores with Task Parallelization, DVFS and Core Consolidation. 126 - Pham Nam Khanh, Akash Kumar, Khin Mi Mi Aung:
Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms. 127-134 - Matthias Freier, Jian-Jia Chen:
Sporadic Task Handling in Time-Triggered Systems. 135-144 - Philipp Ittershagen, Kim Grüttner, Wolfgang Nebel:
A Task-Level Monitoring Framework for Multi-Processor Platforms. 145-152 - Andreas Weichslgartner, Stefan Wildermann, Johannes Götzfried, Felix C. Freiling, Michael Glaß, Jürgen Teich:
Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. 153-162 - Deshya Wijesundera, Alok Prakash, Siew Kei Lam, Thambipillai Srikanthan:
Exploiting Configuration Dependencies for Rapid Area-efficient Customization of Soft-core Processors. 163-172 - Ghassan Shobaki, Najm Eldeen Abu Rmaileh, Jafar Jamal:
Studying the Impact of Bit Switching on CPU Energy. 173-179 - Lin Li, Philipp Wagner, Ramesh Ramaswamy, Albrecht Mayer, Thomas Wild, Andreas Herkersdorf:
A Rule-based Methodology for Hardware Configuration Validation in Embedded Systems. 180-189
Research Presentations
- Alexander Diewald, Sebastian Voss, Simon Barner:
A Lightweight Design Space Exploration and Optimization Language. 190-193 - Christoph W. Kessler, Lu Li, Aras Atalar, Alin Dobre:
An Extensible Platform Description Language Supporting Retargetable Toolchains and Adaptive Execution. 194-196 - Daniele Palossi, Andrea Marongiu:
Exploring Single Source Shortest Path Parallelization on Shared Memory Accelerators. 197-200
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-05 22:23 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
