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ORCIDIntegration, Volume 48
Volume 48, January 2015
- Inna Vaisband
, Eby G. Friedman:
Energy efficient adaptive clustering of on-chip power delivery systems. 1-9 - Maryam Triki, Yanzhi Wang, Ahmed Chiheb Ammari, Massoud Pedram:
Hierarchical power management of a system with autonomously power-managed components using reinforcement learning. 10-20 - Aminollah Mahabadi, Ahmad Khonsari, Behnam Khodabandeloo, Hamid Noori, Alireza Majidi:
Critical path-aware voltage island partitioning and floorplanning for hard real-time embedded systems. 21-35 - Song Jin, Yu Wang, Tongna Liu:
On optimizing system energy of voltage-frequency island based 3-D multi-core SoCs under thermal constraints. 36-45 - Sohaib Majzoub:
Reducing random-dopant fluctuation impact using footer transistors in many-core systems. 46-54 - Julius von Rosen, Felix Salfelder, Lars Hedrich, Benjamin Betting, Uwe Brinkschulte:
A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture. 55-71 - Mario R. Casu, Paolo Mantovani:
A synchronous latency-insensitive RISC for better than worst-case design. 72-82 - Mohammad Mirzaei, Mahdi Mosaffa, Siamak Mohammadi:
Variation-aware approaches with power improvement in digital circuits. 83-100 - Alp Arslan Bayrakci:
Stochastic logical effort as a variation aware delay model to estimate timing yield. 101-108 - Shmuel Wimer, Amnon Stanislavsky:
Energy efficient hybrid adder architecture. 109-115 - Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. 116-128 - Xingbao Zhou, Wai-Shing Luk, Hai Zhou, Fan Yang, Changhao Yan, Xuan Zeng:
Multi-parameter clock skew scheduling. 129-137 - Bo Jiang, Tian Xia:
ADPLL design parameters determinations through noise modeling. 138-145 - Chih-Cheng Hsu, Mark Po-Hung Lin, Yao-Tsung Chang:
Crosstalk-aware multi-bit flip-flop generation for power optimization. 146-157 - Jin-Tai Yan:
Length-constrained escape routing of differential pairs. 158-169 - Hailong Yao, Fan Yang, Yici Cai, Qiang Zhou, Chiu-Wing Sham:
SIAR: Customized real-time interactive router for analog circuits. 170-182 - Nuno Lourenço, António Canelas, Ricardo Povoa, Ricardo Martins, Nuno Horta:
Floorplan-aware analog IC sizing and optimization based on topological constraints. 183-197 - Akram Malak, Yao Li, Ramy Iskander, François Durbin, Farakh Javid, Jean-Marc Guebhard, Marie-Minerve Louërat, André Tissot:
Fast multidimensional optimization of analog circuits initiated by monodimensional global Peano explorations. 198-212 - Vikram Arkalgud Chandrasetty, Syed Mahfuzul Aziz:
Resource efficient LDPC decoders for multimedia communication. 213-220 - Uche Afam Nnolim:
Log-hybrid architecture for tonal correction combined with modified un-sharp masking filter algorithm for colour image enhancement. 221-229 - Shih-Hao Ou, Kuo-Chiang Chang, Chih-Wei Liu:
An energy-efficient, high-precision SFP LPFIR filter engine for digital hearing aids. 230-238
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