


default search action
"Timing-constrained power minimization in VLSI circuits by simultaneous ..."
Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny (2015)
- Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:

Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. Integr. 48: 116-128 (2015)

manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.


Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID













