default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIntegration, Volume 68
Volume 68, September 2019
- Roberto Sierra, Carlos Carreras
, Gabriel Caffarena:
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs. 1-11 - Mohd Syafiq Mispan, Shengyu Duan, Basel Halak, Mark Zwolinski:
A reliable PUF in a dual function SRAM. 12-21 - Yaoyao Ye, Zhe Zhang:
A thermal-sensitive design of a 3D torus-based optical NoC architecture. 22-29 - Lucas Lui Motta, Byron Alejandro Acuña Acurio, Nathália Figueiredo Tinoco Aniceto, Luís Geraldo P. Meloni:
Design and implementation of a digital down/up conversion directly from/to RF channels in HDL. 30-37 - Subhabrata Roy, Abhijit Chandra:
Design of Narrow Transition Band Digital Filter: An Analytical Approach. 38-49 - Farzad Daryabari, Abdulhamid Zahedi, Abbas Rezaei, Mohsen Hayati:
Gain-controlled noise-reduction LNA design using source-bulk resistors and double common-source topology. 50-61 - Boran Wen, Qisheng Zhang, Xiao Zhao, Xiaolong Lv, Yongqing Wang:
Trade-offs among power consumption and other design parameters of two-stage recycling folded cascode OTA that using embedded cascode current buffer compensation technology. 62-70 - Kashif Nawaz, Léopold Van Brandt, Itamar Levi, François-Xavier Standaert, Denis Flandre:
A security oriented transient-noise simulation methodology: Evaluation of intrinsic physical noise of cryptographic designs. 71-79 - Luca Crocetti, Luca Baldanzi, Matteo Bertolucci, Luca Sarti, Berardino Carnevale, Luca Fanucci:
A simulated approach to evaluate side-channel attack countermeasures for the Advanced Encryption Standard. 80-86 - Monir Zaman, Mustafa M. Shihab, Ayse K. Coskun, Yiorgos Makris:
CAPE: A cross-layer framework for accurate microprocessor power estimation. 87-98 - Xiongfei Qu, Ruifeng Liu, Lingling Cao, Yuanzhi Zhang, Wenshen Wang, Huimin Liu, Chao Lu:
A 5.8 GHz digitally configurable DSRC RF-SoC transmitter for China ETC systems. 99-107 - Shady M. Soliman, Mohammed A. Jaela, Abdelrhman Mohamed Abotaleb, Youssef Hassan, Mohamed Abdelghany, Amr Talaat Abdel-Hamid, Khaled N. Salama, Hassan Mostafa:
FPGA implementation of dynamically reconfigurable IoT security module using algorithm hopping. 108-121 - Zhen Wang, Jianhui Jiang, Tao Wang:
Failure probability analysis and critical node determination for approximate circuits. 122-128 - Julián Caba, Fernando Rincón, Julio Dondo, Jesús Barba, Manuel J. Abaldea, Juan Carlos López:
Testing framework for on-board verification of HLS modules using grey-box technique and FPGA overlays. 129-138 - Ferdinando Costanzo, Rocco Giofrè, Antonino Massari, Marziale Feudale, Andrea Suriani, Ernesto Limiti:
A MMIC power amplifier in GaN on Si technology for next generation Q band high throughput satellite systems. 139-146 - Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz:
Simulation environment for link energy estimation in networks-on-chip with virtual channels. 147-156 - Young-Ho Seo, Sung-Ho Park, Dong-Wook Kim:
High-level hardware design of digital comparator with multiple inputs. 157-165
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-05 22:23 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
