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ORCIDMicroprocessing and Microprogramming, Volume 32
Volume 32, Numbers 1-5, August 1991
- Kurt P. Judmann:
Chairman's introduction. vii - Antonio Núñez
:
Program chairman's introduction. ix-x - Session K1: Opening and keynote session. 1
- Session K2: Keynote session. 5
- Session K3: Keynote session. 9
- Session A1: Topics on computer architecture. 11
- Manuel Lois Anido:
Improving the division instruction of application-specific RISCs. 13-21 - Edil S. T. Fernandes, Valmir C. Barbosa, Alberto Ferreira de Souza, Nelson Q. Vasconcelos:
Micro-instruction placement by simulated annealing. 23-28 - B. W. Watson, Willem J. Withagen, M. P. J. Stevens:
Compilation techniques for a high level language processor. 29-36 - Session A2: Multiprocessor. 37
- Samir Bouaziz, Edwige E. Pissaloux, Alain Mérigot, Francis Devos:
A communication mechanism and its implementation in the Multi-SIMD massively parallel machine SPHINX. 39-43 - Júlio Salek Aude, A. J. O. Cruz, Ageu Cavalcanti Pacheco Jr., Alexandre Malheiros Meslin, Gerson Bronstein, G. P. Azevedo, N. R. Figueira, R. P. Azevedo, S. C. Oliveira:
MULTIPLUS: A modular high-performance multiprocessor. 45-52 - Rafael Dueire Lins:
A shared memory architecture for parallel cyclic reference counting. 53-58 - Session A3: Optimization of high speed digital circuits. 59-60
- Luis Ferragut, Rafael Montenegro, G. Winter, Antonio Núñez:
Accurate extraction of interconnect capacitances by adaptive mixed F.E.M. 61-68 - Veronika Eisele, Doris Schmitt-Landsiedel:
Optimization and architectural evaluation of regular combinatoric structures. 69-73 - K. Eshraghian, Roberto Sarmiento, Pedro P. Carballo, Antonio Núñez:
Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation. 75-82 - Session A4: Object orientied VLSI design. 83-84
- Wlodzimierz Wrona, Adam Pawlak:
VLSI integrated circuit design representation in an object-oriented CAD environment. 85-92 - Colin C. Charlton, Paul H. Leng, Mark Rivers:
Object-oriented modelling in digital circuit CAD systems. 93-100 - Yun-Chao Hu, Ad Verschueren, M. P. J. Stevens:
Object oriented system analysis for VLSI. 101-108 - Session B1: Design and testing of real-time systems. 109
- J. S. Sagoo, D. J. Holding:
A comparison of temporal Petri net techniques in the specification and design of hard real-time systems. 111-118 - Peng Tu, Kwei-Jay Lin:
Minimizing the maximum lateness in real-time computations with extended deadlines. 119-126 - Hannu Honka, Matti Kattilakoski:
A simulation-based system for testing real-time embedded software in the host environment. 127-134 - Fred Hemery, Dominique Lazure, Eric Delattre, Jean-François Méhaut:
An analysis of communication and multiprogramming in the Helios operating system. 137-144 - Shang-Rong Tsai, Ru Jing Chen:
Interprocess communication with multicast support in DMINIX operating system. 145-152 - Franck Delaplace, Jean-Louis Giavitto:
An efficient routing strategy to support process migration. 153-160 - Session B3: Hardware building block. 161
- R. Rauscher, V. Grupe:
Use of mathematical procedures for the task of power measurement and the corresponding VLSI-realization. 163-169 - Jean-Luc Béchennec, Franck Cappello, Daniel Etiemble:
3D hardware packages for parallel architectures. 171-177 - Jean-Luc Peter:
Design of a custom dram storage unit coupled to i486(tm). 179-181 - Session B4: VLSI synthesis. 183
- J. Septiéna, Daniel Mozos, Román Hermida, Francisco Tirado:
A hardware allocator guided by cost functions. 185-192 - H.-G. Haeck, F. Krohm, Yiannos Manoli:
Data path synthesis from a microcontroller instruction set specification in microsyn. 193-198 - Jordi Cortadella, Rosa M. Badia, Eduard Ayguadé:
Scheduling in a continuous area-time design space. 199-206 - Session C1: CMOS implementation of the IBM ESA/390. 207
- Nicholas Roethe, Udo Wille:
A CMOS implementation of the ESA/390 mainframe architecture. 209-214 - Gerhard Döttling:
Data consistency in a multiprocessor system with 'store in' cache concept. 215-219 - Dietmar Schmunkamp:
The clock, test and maintenance control chip of the IBM ES/9221. 221-226 - A. Tietz, J. Koehl:
A VLSI - CAD system for efficient design of CMOS/390 processors. 227-234 - Mario Dal Cin:
Fault tolerance for highly parallel computers. 237-241 - V. Lakshmi Narasimhan, Tom Downs:
Fault tolerant aspects of a dynamic dataflow architecture - PATTSY. 243-252 - Andreas Steininger, Herbert Schweinzer:
Towards an optimal combination of error detection mechanisms. 253-259 - Session C3: Advances in object oriented design. 261
- Massimo Ancona, Gabriele Nani, Maddali Paci:
An object oriented approach to data persistence. 263-270 - Alexander Schill:
Language and runtime support for distributed object groups. 271-279 - K. C. Huang, W. S. Hsieh, C. S. Lu, M. S. Yang, T. S. Nain, Ihnen Lin:
Implementation and design of PVD: An interactive protocol specification and validation environment. 281-288 - A. T. Balou, Apostolos Nikolaos Refenes:
The design and implementation of VOOM: a parallel virtual Object Oriented machine. 289-296 - Session C4: Architectural Synthesis. 297
- Manfred Schäfer, Georg Klein-Heßling:
A design concept for verified concurrent controllers. 299-306 - Panagiotis Tsanakas, George K. Papakonstantinou, Stefanos Kaxiras:
A Prolog-based design environment for the high-level synthesis of application-specific architectures. 307-313 - Stefano Antoniazzi, Mirella Mastretti:
An architectural design support environment for high-performance digital systems. 315-321 - L. P. M. Benders, M. P. J. Stevens:
Task level behavioral hardware description. 323-331 - Jürgen Büddefeld, Karl-Erwin Grosspietsch, Bedrich J. Hosticka, Roland Klinkel, G. Wagner:
An intelligent sensor integrated preprocessing facility for neural networks. 335-341 - Vítor Silva, Luis Cruz, F. Lopes, A. Rodrigues, L. de Sá:
Multiprocessor based image coding. 343-348 - Cesare Alippi:
The determination of angular values and parameters in flat surfaces: from the mathematical approach to the CORDIC architecture. 349-355 - Session D2: Fault tolerant parallel software. 357
- Gilles Muller, Bruno Rochat, Patrick Sanchez:
A stable transactional memory for building robust object oriented programs. 359-363 - Session D2: Fault tolerant parallel software. 365-372
- Session D2: Fault tolerant parallel software. 373-380
- Session D3: Program development environments. 381
- S. El-Kassas:
Visual languages their definition and applications in system development. 383-391 - Valmir C. Barbosa, Lúcia Maria de A. Drummond, Astrid Luise H. Hellmuth:
An integrated software environment for large-scale Occam programming. 393-400 - Miguel Angel Ruz Fernández, Gonzalo León Serrano, María Victoria Elbal Díaz:
An integrated framework for the design of distributed programming environments. 401-409 - Session D4: VLSI design and routing. 411
- Fermín Calvo Torre:
From a high level description of an IC to silicium: Don't loose design intent. 413-415 - Michal Servít, Jan Schmidt:
Strategy of one and half layer routing. 417-423 - N. A. Kyrloglou, S. Koutroubinas, A. Koyandis, Constantinos E. Goutis:
A placing and routing tool implemented in Prolog. 425-433 - Session E1: Image recognition. 435
- Apostolos Nikolaos Refenes, Cesare Alippi:
Iiistological image understanding by error backpropagation. 437-446 - Jukka Neejärvi, Viktor Fischer, Sakari Alenius, Yrjö Neuvo:
Knowledge-based segmentation using morphological filters. 447-452 - Roberto Jezieniecki, Eduardo Rovaris:
An image distance measure insensitive to amplitude and mean value variations: Application to data reduction through SVD. 453-460 - Session E2: Parallel program development. 461
- Theo Ungerer:
Parallelising C++-programs for transputer systems. 463-470 - Péter Kacsuk:
Implementing Prolog on a DAP/Multi-transputer computer. 471-478 - Emilio Luque, Remo Suppi, Joan Sorribes, M. A. Mayosky, Miquel A. Senar:
Simulation and visualization tools for link-based parallel architectures. 479-486 - Session E3: Prolog. 487
- H. Sorensen, T. A. Delaney, W. P. Kenneally, S. J. M. Murphy, F. B. O'Flaherty, A. B. O'Mahony, D. M. J. Power:
Towards a development environment for fifth generation systems. 489-496 - Gilles Berger-Sabbatel, Abderrazak Jemai:
Prolog on a RISC: Implementation and evaluation. 497-504 - Hendrik C. R. Lock, Anamaria Martins:
Issues in the implementation of Prolog, and their optimization. 505-514 - Session E4: Hardware description languages. 515
- Roy D. Dowsing, R. Elliott:
A higher level of behavioural specification: An example in interval temporal logic. 517-524 - József Sziray, Zsolt Nagy:
Opart: A hardware-description language for test generation. 525-530 - R. J. Huis in 't Veld:
Formalizing the design-trajectory of sequential machines. 531-538 - Session F1: Digital signal processing. 539
- Alois C. Knoll, Markus Freericks:
An applicative real-time language for DSP-programming supporting asynchronous data-flow concepts. 541-547 - Christine Dours-Senac:
Temporal control improvement of hidden Markov models for automatic speech recognition. 549-556 - Spiros Nikolaidis, Odysseas G. Koufopavlou, Sergios Theodoridis, Constantinos E. Goutis:
Array processor for LS FIR system identification. 557-563 - Kyösti Rautiola, Pekka Jokitalo:
DSP-architecture design with a Petri-net-based simulator. 565-572 - Session F2: Interconnection networks for multiprocessors. 573
- Imrich Chlamtac, Aura Ganz, Martin G. Kienzle:
Control policies for interconected distributed systems via an HIPPI switch. 575-582 - C. S. Yang, W. S. Hsieh, Der-Chyuan Lou, J. S. Tzeng:
A regular interconnection network. 583-587 - C. S. Yang, S. Y. Wu, K. C. Huang:
A reconfigurable modular fault tolerant generalized Boolean n-cube network. 589-592 - Gerard J. M. Smit, Paul J. M. Havinga, Pierre G. Jansen, Fokke de Boer, Bert Molenkamp:
On hardware for generating routes in Kautz digraphs. 593-599 - Session F3: System design. 601
- Franz Lehner:
Software life cycle management based on a phase distinction method. 603-608 - Ernest Wallmüller:
Software quality management. 609-616 - Krzysztof Sacha:
Transnet: A method for transformational development of embedded software. 617-624 - Javier Miranda, José Fortes Gálvez:
A modula-2-like systems programming language and its implementation. 625-634 - D. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne:
TVA: A timing verifier with analytic temporal modelling. 637-644 - Thomas Müller-Wipperfürth, Hermann Hellwagner, Franz Pichler:
LISAS - Simulation tool for regular networks of finite state machines. 645-650 - Thomas Müller-Wipperfürth, Hermann Hellwagner, Franz Pichler:
LISAS - Simulation tool for regular networks of finite state machines. 651-656 - Lech Józwiak, J. C. Kolsteren:
An efficient for the sequential general decomposition of sequential machines. 657-664 - Session F5: The ESPRIT-PATRICIA project. 665
- Eleanor M. Mayger, M. D. Francis, R. L. Harris, Gerry Musgrave, Michael P. Fourman:
The need for a core method DIALOG - Linking formal proof to the design environment. 667-673 - M. Hadjinicolaeu, N. Burgess, Donatella Sciuto, G. Buananno, Patrizia Cavalloro, Giuseppe Zaza:
The Patricia testability analysis tool. 675-682 - Anna Antola, Fausto Distante:
DFG: a graph based approach for algorithmic flow driven architecture synthesis. 683-690 - Robert M. Zimmer, Alan J. MacDonald, Robert Holte:
CAD for verified hardware design via category theory. 691-698 - Session G1: Control applications. 699-700
- D. P. Kwok, P. Wang, C. K. Li:
A combined fuzzy and classical PID controller. 701-708 - Herbert Schweinzer, Günther Stadlbauer:
A multiprocessor bus system with cyclic data exchange for the field of control and signal processing. 709-716 - Raimund Mitterbauer:
Concept for aelf-calibrating floatingpoint-converter for audio-applications. 717-719 - Session G2: Network communication protocols. 721
- W. S. Hsieh, T. S. Nain, M. S. Yang, C. S. Lu, K. C. Huang, J. R. Tseng:
A fast method of protocol validation using reduced stable state exploration technique. 723-730 - Monika Kapus-Kolar:
Deriving protocol specifications from service specifications including parameters. 731-738 - Stephen P. Van Trees, Ophir Frieder:
On the specification and implementation of X.25 using CSP and OCCAM. 739-744 - Session G3: Database systems. 745
- Jong T. Lim, Song C. Moon:
Global checkpointing scheme for heterogeneous distributed database systems. 747-754 - Achilles Kameas, Panagiotis Fitsilis, Georgios Pavlides:
Algorithms for inference control. 755-764 - Byung Y. Hwang, Byung W. Kim, Song C. Moon:
Efficient access method for multi-dimensional complex objects in spatial databases: BR tree. 765-772 - Session G4: VLSI testing and modelling I. 773
- Giacomo Buonanno, Fabrizio Lombardi, Donatella Sciuto, Y.-N. Sken:
Multiple stuck-at faults detection in CMOS combinational gates. 775-782 - François Darlay:
Detection of multiple stuck-on/stuck-open faults by single faults test sets in MOS transistor networks. 783-789 - Uwe Hübner, H. Hinsen, M. Hofebauer, Heinrich Theodor Vierhaus:
Mixed level test generation for high fault coverage. 791-796 - Session H1: Quality control. 797
- Eugen Brenner, J. Grabner, M. Moosburger, G. Otschko, K. Schlögl, P. Seifter, J. Song, Christian Steger, Reinhold Weiss:
Design and implementation of a distributed real-time expert-system for fault diagnosis in modular manufacturing systems. 799-806 - István Erényi, Judit Pongrácz:
Quality control in textile industry via machine vision. 807-813 - Session H2: Evaluation of parallel systems. 815
- Yehuda Wallach, E. Yaprak:
Parallel solution of state-estimation on an IBM ring network. 817-824 - Agustín Fernández, José María Llabería, Juan J. Navarro, Miguel Valero-García:
Performance evaluation of transputer systems with linear algebra problems. 825-832 - Session H3: Testing methods. 833
- Xinli Gu, Krzysztof Kuchcinski, Zebo Peng:
Testability measure with reconvergent fanout analysis and its applications. 835-842 - András Pataricza:
Remarks on the use of Reed-Solomon codes in signature analysis. 843-850 - Session H4: VLSI testing and fault modelling II. 851
- M. J. Aguado, J. L. Conesa, E. de la Torre, J. Uceda:
A new approach on fault list handling for faster fault elimination and direct test vector generation. 853-859 - Guy A. S. Wingate, Clive Preece:
Analysis of failure data collected from a TMR microprocessor controller. 861-868
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