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ORCIDMicroprocessors and Microsystems, Volume 36
Volume 36, Number 1, February 2012
- Kishor Sarawadekar, Harihar Bharat Indana, Deep Bera, Swapna Banerjee:
VLSI-DSP based real time solution of DSC-SRI for an ultrasound system. 1-12 - Fatih Say, Cüneyt F. Bazlamaçci
:
A reconfigurable computing platform for real time embedded applications. 13-32 - Prodromos Chatziagorakis, Georgios Ch. Sirakoulis, John N. Lygouras:
Design automation of cellular neural networks for data fusion applications. 33-44 - Robert Czerwinski, Dariusz Kania:
Area and speed oriented synthesis of FSMs for PAL-based CPLDs. 45-61
Volume 36, Number 2, March 2012
- Ramon Doallo, Margarita Amor, Basilio B. Fraguela:
Special issue editorial: Exploitation of hardware accelerators. 63-64 - Juan Carlos Pichel, Francisco F. Rivera, Marcos Fernández, Aurelio Rodríguez:
Optimization of sparse matrix-vector multiplication using reordering techniques on GPUs. 65-77 - Ruymán Reyes, Francisco de Sande:
Optimization strategies in different CUDA architectures using llCoMP. 78-87 - Jose Rodrigo Sanjurjo, Margarita Amor, Montserrat Bóo, Ramon Doallo:
High-performance Monte Carlo radiosity on GPU based on scene partitioning. 88-95 - Nuno Sebastião, Nuno Roma, Paulo F. Flores:
Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase. 96-109 - Tobias Schumacher, Christian Plessl, Marco Platzner:
IMORC: An infrastructure and architecture template for implementing high-performance reconfigurable FPGA accelerators. 110-126 - Uwe Meyer-Bäse, Guillermo Botella Juan, Soumak Mookherjee, Encarnación Castillo, Antonio García:
Energy optimization of Application-Specific Instruction-Set Processors by using hardware accelerators in semicustom ICs technology. 127-137 - Antony W. Savich, Medhat Moussa, Shawki Areibi:
A scalable pipelined architecture for real-time computation of MLP-BP neural networks. 138-150
Volume 36, Number 3, May 2012
- Shahin Sanayei Lotfabadi, Andy Gean Ye, Sridhar Krishnan:
Measuring the power efficiency of subthreshold FPGAs for implementing portable biomedical applications. 151-158 - Merve Peyic, Hakan Baba, Erdem Guleyuboglu, Ilker Hamzaoglu, Mehmet Keskinöz:
A low power multi-rate decoder hardware for IEEE 802.11n LDPC codes. 159-166 - Omesh Mutukuda, Andy Gean Ye, Gul N. Khan:
Utilizing multi-bit connections to improve the area efficiency of unidirectional routing resources for routing multi-bit signals on FPGAs. 167-175 - Rabie Ben Atitallah, Éric Piel, Smaïl Niar, Philippe Marquet, Jean-Luc Dekeyser:
A fast MPSoC virtual prototyping for intensive signal processing applications. 176-189 - Grigorios Mingas, Emmanouil G. Tsardoulias, Loukas Petrou:
An FPGA implementation of the SMG-SLAM algorithm. 190-204 - Yusuf Adibelli, Mustafa Parlak, Ilker Hamzaoglu:
Computation and power reduction techniques for H.264 intra prediction. 205-214 - Grigorios Chrysos, Apostolos Dollas, Nikolaos G. Bourbakis:
An embedded software-reconfigurable color segmentation architecture for image processing systems. 215-231 - María José Canet, Javier Valls, Vicenç Almenar, José Marín-Roig:
FPGA implementation of an OFDM-based WLAN receiver. 232-244 - M. Tamagnone, Maurizio Martina, Guido Masera:
An application specific instruction set processor based implementation for signal detection in multiple antenna systems. 245-256 - Gyu Sang Choi, Ingyu Lee, Mankyu Sung, Choongjae Im:
A hybrid SSD with PRAM and NAND Flash memory. 257-266 - Po-Yueh Chen, Chao-Chin Wu, Ying-Jie Jiang:
Bitmask-based code compression methods for balancing power consumption and code size for hard real-time embedded systems. 267-279
Volume 36, Number 4, June 2012
- Paolo Zicari, Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
Low-cost FPGA stereo vision system for real time disparity maps calculation. 281-288 - Girma S. Tewolde, Darrin M. Hanna, Richard E. Haskell:
A modular and efficient hardware architecture for particle swarm optimization algorithm. 289-302 - Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar:
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design. 303-314 - Zheng Ding, Feng Zhao, Wei Shu, Min-You Wu:
Face detection system for SVGA source with hecto-scale frame rate on FPGA board. 315-323 - Dongdong Chen, Seok-Bum Ko:
A dynamic non-uniform segmentation method for first-order polynomial function evaluation. 324-332
Volume 36, Number 5, July 2012
- José Francisco López, Roberto Sarmiento:
Special Issue on Design of Circuits and Integrated Systems. 333 - Marta Portela-García, Michelangelo Grosso, M. Gallardo-Campos, Matteo Sonza Reorda, Luis Entrena, Mario García-Valderas, Celia López-Ongil:
On the use of embedded debug features for permanent and transient fault resilience in microprocessors. 334-343 - David Cuesta, José Luis Risco-Martín, José L. Ayala:
3D thermal-aware floorplanner using a MILP approximation. 344-354 - Stepan Sutula, Carles Ferrer, Francisco Serra-Graells:
Design and modeling of a low-power multi-channel integrated circuit for infrared gas recognition. 355-364 - Miguel Lino Silva, João Canas Ferreira:
Run-time generation of partial FPGA configurations for subword operations. 365-374 - Todor Mladenov, Saeid Nooshabadi, Juan A. Montiel-Nelson, Keseon Kim:
Decoding of Raptor codes on embedded systems. 375-382 - Jesús Barba, Fernando Rincón, Francisco Moya, Julio Dondo, Juan Carlos López:
A comprehensive integration infrastructure for embedded system design. 383-392 - Ana Cinta Oria, Vicente Baena, Joaquín Granado, Jorge Chávez, Patricio López, José García Doblado, Darío Pérez-Calderón:
Reduced complexity ICI cancellation scheme for OFDM DVB-SH receivers. 393-401 - Julian Viejo, Jose Ignacio Villar, Jorge Juan, Alejandro Millán, Enrique Ostúa, Juan Quiros:
Long-term on-chip verification of systems with logical events scattered in time. 402-408 - Haridimos T. Vergos, Dimitris Bakalis:
Area-time efficient multi-modulus adders and their applications. 409-419 - Nivard Aymerich, Antonio Rubio:
Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy. 420-426 - Rubén Salvador, Alberto Vidal, Félix Moreno, Teresa Riesgo, Lukás Sekanina:
Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling. 427-438 - Jesús M. Pérez, Pablo González de Aledo, Pablo Sánchez Espeso:
Real-time voxel-based visual hull reconstruction. 439-447
Volume 36, Number 6, August 2012
- Faizal Arya Samman, Thomas Hollstein, Manfred Glesner:
Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method. 449-461 - Bernhard Fechner:
Fast online error detection and correction with thread signature calculae. 462-470 - Santanu Kundu, Soumya J., Santanu Chattopadhyay:
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router. 471-488 - Jiang-Bo Qian, Youming Li, Yongli Wang, Huahui Chen, Yihong Dong:
An embedded co-processor for accelerating window joins over uncertain data streams. 489-504 - Xingang Ju, Liang Yang:
Performance analysis and comparison of 2 × 4 network on chip topology. 505-509 - Suxia Zhu, Zhenzhou Ji, Tao Liu, Qing Wang:
CCTR: An efficient point-to-point memory race recorder implemented in chunks. 510-519 - Qiyue Li, Jie Li, Jianping Wang, Baohua Zhao, Yugui Qu:
A pipelined processor architecture for regular expression string matching. 520-526 - Faizal Arya Samman, Thomas Hollstein, Manfred Glesner:
Erratum to Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method Microprocessors and Microsystems (2012) 449-461. 527
Volume 36, Number 7, October 2012
- Hamid Sarbazi-Azad, Nader Bagherzadeh:
Editorial notes: Special issue on on-chip parallel and network-based systems. 529-530 - Farshad Safaei, Majed ValadBeigi:
An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip. 531-542 - Spiridon F. Beldianu, Christopher Dahlberg, Timothy Steele, Sotirios G. Ziavras:
Versatile design of shared vector coprocessors for multicores. 543-554 - Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh:
A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms. 555-570 - Dara Rahmati, Hamid Sarbazi-Azad, Shaahin Hessabi, Abbas Eslami Kiasari:
Power-efficient deterministic and adaptive routing in torus networks-on-chip. 571-585
Volume 36, Number 8, November 2012
- Andreas Koch, Roger F. Woods:
Preface - ARC. 587 - Umer Farooq, Husain Parvez, Habib Mehrez, Zied Marrakchi:
A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. 588-605 - Christophe Alias, Bogdan Pasca, Alexandru Plesco:
FPGA-specific synthesis of loop-nests with pipelined computational cores. 606-619 - Oriol Arcas, Nehir Sönmez, Gokhan Sayilar, Satnam Singh, Osman S. Unsal, Adrián Cristal, Ibrahim Hur, Mateo Valero:
Resource-bounded multicore emulation using Beefarm. 620-631 - Sascha Mühlbach, Andreas Koch:
NetStage/DPR: A self-reconfiguring platform for active and passive network security operations. 632-643 - Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition. 644-664 - Samuel Bayliss, George A. Constantinides:
Analytical synthesis of bandwidth-efficient SDRAM address generators. 665-675 - Stefan Schulze, Sergej Sawitzki:
Processor design using a functional hardware description language. 676-694 - Pavel G. Zaykov, Georgi Kuzmanov:
Multithreading on reconfigurable hardware: An architectural approach. 695-704
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