default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDThe Journal of VLSI Signal Processing, Volume 21
Volume 21, Number 1, May 1999
- M. Kivioja, Jouni Isoaho, L. Vänskä:
Design and Implementation of Viterbi Decoder with FPGAs. 5-14 - Ding-Ming Kwai, Behrooz Parhami:
Scalability of Programmable FIR Digital Filters. 31-35 - Hosahalli R. Srinivas, Keshab K. Parhi
:
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture. 37-60 - Shousheng He, Mats Torkelson:
An Orthogonal Time-Frequency Extraction Approach to 2D Systolic Architecture for 1D DFT Computation. 61-70
Volume 21, Number 2, June 1999
- Valerie E. Taylor:
Guest Editor's Introduction. 75 - Peter Rieder, Sven Simon, Christian V. Schimpfle:
Application Specific Efficient VLSI Architectures for Orthogonal Single- and Multiwavelet Transforms. 77-90 - Manuel Sánchez, Juan López, Oscar G. Plata, María A. Trenas, Emilio L. Zapata:
An Efficient Architecture for the In-Place Fast Cosine Transform. 91-102 - Andy Negoi, Stefan Bara, Jacques Zimmermann, Alain Guyot:
A Dedicated Circuit for Charged Particles Simulation Using the Monte Carlo Method. 103-116 - Benjamin W. Wah, Zhe Wu:
Discrete Lagrangian Methods for Designing Multiplierless Two-Channel PR-LP Filter Banks. 131-149 - Shuvra S. Bhattacharyya, Praveen K. Murthy, Edward A. Lee:
Synthesis of Embedded Software from Synchronous Dataflow Specifications. 151-166 - James E. Stine, Michael J. Schulte:
The Symmetric Table Addition Method for Accurate Function Approximation. 167-177
Volume 21, Number 3, July 1999
- Asim Smailagic, Hugo De Man:
Guest Editors' Introduction. 183-184 - Diederik Verkest, Julio Leao da Silva Jr., Chantal Ykman-Couvreur, Kris Croes, Miguel Miranda, Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Hugo De Man:
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management. 185-194 - Jeff Y. F. Hsieh, Teresa H.-Y. Meng:
Low-Power Parallel Video Compression Architecture for a Single-Chip Digital CMOS Camera. 195-207 - William E. Dougherty, David J. Pursley, Donald E. Thomas:
Subsetting Behavioral Intellectual Property for Low Power ASIP Design. 209-218 - Francky Catthoor:
Energy-Delay Efficient Data Storage and Transfer Architectures and Methodologies: Current Solutions and Remaining Problems. 219-231 - Tamal Mukherjee, Gary K. Fedder:
Hierarchical Mixed-Domain Circuit Simulation, Synthesis and Extraction Methodology for MEMS. 233-249 - Asim Smailagic, Daniel P. Siewiorek:
System Level Design as Applied to CMU Wearable Computers. 251-263 - Heebyung Yoon, Junwei Hou, Swapan K. Bhattacharya, Abhijit Chatterjee, Madhavan Swaminathan:
Fault Detection and Automated Fault Diagnosis for Embedded Integrated Electrical Passives. 265-276 - Wolfgang Boßung, Sorin Alexander Huss, Stephan Klaus:
High-Level Embedded System Specifications Based on Process Activation Conditions. 277-291
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-04 22:08 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
