Chia-Lin Yang

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Hsiang-Pang Li

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Publications

2022
[j29]
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Wei-Ting Lin, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, Chin-Fu Nien:
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators. ACM Trans. Embed. Comput. Syst. 21(3): 24:1-24:29 (2022)
[c74]
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  - conf/nvmsa/DongCYLL22
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Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang, Bo-Rong Lin, Hsiang-Pang Li:
Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging. NVMSA 2022: 1-7
2019
[c64]
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  - conf/isca/YangCYTHCL19
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Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li:
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. ISCA 2019: 236-249
2018
[c61]
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  - conf/iccad/LinCLYTYHCLC18
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Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang:
DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. ICCAD 2018: 31
2017
[j24]
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  - journals/todaes/LinYLW17
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Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang:
A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration. ACM Trans. Design Autom. Electr. Syst. 22(2): 27:1-27:22 (2017)
2016
[j23]
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  - journals/tc/LiuCYLHL16
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Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li:
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality. IEEE Trans. Computers 65(4): 1090-1102 (2016)
2015
[c54]
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  - conf/islped/LaiYYL15
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Chun-Hao Lai, Shun-Chih Yu, Chia-Lin Yang, Hsiang-Pang Li:
Fine-grained write scheduling for PCM performance improvement under write power budget. ISLPED 2015: 19-24
[c52]
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  - conf/nvmsa/LinYLW15
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Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang:
A buffer cache architecture for smartphones with hybrid DRAM/PCM memory. NVMSA 2015: 1-6
2014
[c49]
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  - conf/dac/LiuCYLHL14
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Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li:
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs. DAC 2014: 145:1-145:6

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