Liang-Hung Lu

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Jun-Chau Chien

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Publications

2007
[j5]
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Huei-Yan Huang, Jun-Chau Chien, Liang-Hung Lu:
A 10-Gb/s Inductorless CMOS Limiting Amplifier With Third-Order Interleaving Active Feedback. IEEE J. Solid State Circuits 42(5): 1111-1120 (2007)
[j4]
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Jun-Chau Chien, Liang-Hung Lu:
Analysis and Design of Wideband Injection-Locked Ring Oscillators With Multiple-Input Injection. IEEE J. Solid State Circuits 42(9): 1906-1915 (2007)
[j3]
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Jun-Chau Chien, Liang-Hung Lu:
Design of Wide-Tuning-Range Millimeter-Wave CMOS VCO With a Standing-Wave Architecture. IEEE J. Solid State Circuits 42(9): 1942-1952 (2007)
[j2]
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Jun-Chau Chien, Liang-Hung Lu:
40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-µm CMOS. IEEE J. Solid State Circuits 42(12): 2715-2725 (2007)
[c7]
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  - conf/isscc/ChienL07
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Jun-Chau Chien, Liang-Hung Lu:
40Gb/s High-Gain Distributed Amplifiers with Cascaded Gain Stages in 0.18μm CMOS. ISSCC 2007: 538-620
[c6]
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Jun-Chau Chien, Liang-Hung Lu:
40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18μm CMOS. ISSCC 2007: 544-621
2005
[c3]
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  - conf/cicc/ChenCL05
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Tai-Yuan Chen, Jun-Chau Chien, Liang-Hung Lu:
A 45.6-GHz matrix distributed amplifier in 0.18-nm CMOS. CICC 2005: 119-122

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