Hung-Ming Chen

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Hao-Yu Chi

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Publications

2023
[j54]
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A. K. Thasreefa, Abhishek Patyal, Hao-Yu Chi, Mark Po-Hung Lin, Hung-Ming Chen:
On Reducing LDE Variations in Modern Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(4): 1268-1279 (2023)
2022
[c101]
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  - conf/date/ChiCCLKCH22
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Hao-Yu Chi, Simon Yi-Hung Chen, Hung-Ming Chen, Chien-Nan Liu, Yun-Chih Kuo, Ya-Hsin Chang, Kuan-Hsien Ho:
Practical Substrate Design Considering Symmetrical and Shielding Routes. DATE 2022: 951-956
2021
[j49]
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  - journals/tcad/ChiLHLC21
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Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen:
A Style-Based Analog Layout Migration Technique With Complete Routing Behavior Preservation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(12): 2556-2567 (2021)
2020
[j46]
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  - journals/todaes/ChiLC20
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Hao-Yu Chi, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Wire Load Oriented Analog Routing with Matching Constraints. ACM Trans. Design Autom. Electr. Syst. 25(6): 55:1-55:26 (2020)
[c88]
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  - conf/iccad/LinCPLZLC20
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Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Achieving Analog Layout Integrity through Learning and Migration Invited Talk. ICCAD 2020: 55:1-55:8
2019
[c81]
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  - conf/iccad/ChiLHLC19
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Hao-Yu Chi, Zi-Jun Lin, Chia-Hao Hung, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines. ICCAD 2019: 1-6
[c78]
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  - conf/smacd/ChenCSLC19
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Yu-Hsien Chen, Hao-Yu Chi, Ling-Yen Song, Chien-Nan Jimmy Liu, Hung-Ming Chen:
A Structure-Based Methodology for Analog Layout Generation. SMACD 2019: 33-36
2018
[c75]
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  - conf/aspdac/ChiTLC18
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Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu, Hung-Ming Chen:
Performance-preserved analog routing methodology via wire load reduction. ASP-DAC 2018: 482-487
[c74]
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  - conf/dac/PatyalPACCL18
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Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu:
Analog placement with current flow and symmetry constraints using PCP-SP. DAC 2018: 10:1-10:6

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