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ORCIDMichael Laurenzano
- > Home > Persons > Michael Laurenzano
Publications
- 2016
[j8]Joshua Peraza, Ananta Tiwari, Michael Laurenzano, Laura Carrington, Allan Snavely:
PMaC's green queue: a framework for selecting energy optimal DVFS configurations in large scale MPI applications. Concurr. Comput. Pract. Exp. 28(2): 211-231 (2016)- [j7]Alex D. Breslow, Leo Porter
, Ananta Tiwari, Michael Laurenzano, Laura Carrington, Dean M. Tullsen, Allan Snavely:
The case for colocation of high performance computing workloads. Concurr. Comput. Pract. Exp. 28(2): 232-251 (2016) - [c29]Michael A. Laurenzano, Ananta Tiwari, Allyson Cauble-Chantrenne, Adam Jundt, William A. Ward Jr., Roy L. Campbell, Laura Carrington:
Characterization and bottleneck analysis of a 64-bit ARMv8 platform. ISPASS 2016: 36-45 - 2015
- [j4]Michael A. Laurenzano, Joshua Peraza, Laura Carrington, Ananta Tiwari, William A. Ward Jr., Roy L. Campbell:
PEBIL: binary instrumentation for practical data-intensive program analysis. Clust. Comput. 18(1): 1-14 (2015) - [c19]Adam Jundt, Allyson Cauble-Chantrenne, Ananta Tiwari, Joshua Peraza, Michael A. Laurenzano, Laura Carrington:
Compute bottlenecks on the new 64-bit ARM. E2SC@SC 2015: 6:1-6:7 - [c18]Ananta Tiwari, Kristopher Keipert, Adam Jundt, Joshua Peraza, Sarom S. Leang, Michael Laurenzano, Mark S. Gordon, Laura Carrington:
Performance and energy efficiency analysis of 64-bit ARM using GAMESS. Co-HPC@SC 2015: 8:1-8:10 - 2014
- [j3]Leo Porter, Michael A. Laurenzano, Ananta Tiwari, Adam Jundt, William A. Ward Jr., Roy L. Campbell, Laura Carrington:
Making the Most of SMT in HPC: System- and Application-Level Perspectives. ACM Trans. Archit. Code Optim. 11(4): 59:1-59:26 (2014) - [c17]Ananta Tiwari, Anthony Gamst, Michael A. Laurenzano, Martin Schulz, Laura Carrington:
Modeling the Impact of Reduced Memory Bandwidth on HPC Applications. Euro-Par 2014: 63-74 - [c16]Michael A. Laurenzano, Ananta Tiwari, Adam Jundt, Joshua Peraza, William A. Ward Jr., Roy L. Campbell, Laura Carrington:
Characterizing the Performance-Energy Tradeoff of Small ARM Cores in HPC Computation. Euro-Par 2014: 124-137 - 2013
- [j2]Laura Carrington, Michael Laurenzano, Ananta Tiwari:
Characterizing Large-Scale HPC Applications through Trace extrapolation. Parallel Process. Lett. 23(4) (2013) - [c13]Joshua Peraza, Ananta Tiwari, Michael Laurenzano, Laura Carrington, William A. Ward Jr., Roy L. Campbell:
Understanding the performance of stencil computations on Intel's Xeon Phi. CLUSTER 2013: 1-5 - [c12]Laura Carrington, Michael Laurenzano, Ananta Tiwari:
Inferring Large-Scale Computation Behavior via Trace Extrapolation. IPDPS Workshops 2013: 1667-1674 - 2012
- [c11]Ananta Tiwari, Michael Laurenzano, Joshua Peraza, Laura Carrington, Allan Snavely:
Green Queue: Customized Large-Scale Clock Frequency Scaling. CGC 2012: 260-267 - [c10]Ananta Tiwari, Michael Laurenzano, Laura Carrington, Allan Snavely:
Modeling Power and Energy Usage of HPC Kernels. IPDPS Workshops 2012: 990-998 - [c9]Michael Laurenzano, Joshua Peraza, Laura Carrington, Ananta Tiwari, William A. Ward Jr., Roy L. Campbell:
A Static Binary Instrumentation Threading Model for Fast Memory Trace Collection. SC Companion 2012: 741-745 - [c8]Kayla O. Seager, Ananta Tiwari, Michael Laurenzano, Joshua Peraza, Pietro Cicotti, Laura Carrington:
Efficient HPC Data Motion via Scratchpad Memory. SC Companion 2012: 801-805 - 2011
- [c6]Ananta Tiwari, Michael Laurenzano, Laura Carrington, Allan Snavely:
Auto-tuning for Energy Usage in Scientific Applications. Euro-Par Workshops (2) 2011: 178-187
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