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2010 – 2019
- 2018
[j3]Hiroki Hihara
, Akira Iwasaki, Masanori Hashimoto, Hiroyuki Ochi, Yukio Mitsuyama, Hidetoshi Onodera, Hiroyuki Kanbara, Kazutoshi Wakabayashi, Tadahiko Sugibayashi, Takashi Takenaka, Hiromitsu Hada, Munehiro Tada, Makoto Miyamura, Toshitsugu Sakamoto:
Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. IEEE Embed. Syst. Lett. 10(4): 119-122 (2018)- [c4]Yuuki Oosako, Nagisa Ishiura, Hiroyuki Tomiyama, Hiroyuki Kanbara:
Synthesis of Full Hardware Implementation of RTOS-Based Systems. RSP 2018: 1-7 - 2017
- [c3]Kagumi Azuma, Nagisa Ishiura, Nobuaki Yoshida, Hiroyuki Kanbara:
Distributed memory architecture for high-level synthesis of embedded controllers from Erlang. Erlang Workshop 2017: 13-19 - [c2]Naoya Ito, Yuuki Oosako, Nagisa Ishiura, Hiroyuki Kanbara, Hiroyuki Tomiyama:
Binary synthesis implementing external interrupt handler as independent module. RSP 2017: 92-98 - 2015
- [c1]Masanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera:
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. ASP-DAC 2015: 14-15 - 2014
- [j2]Hiroaki Konoura, Dawood Alnajiar, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Masanori Hashimoto, Takao Onoye, Hidetoshi Onodera:
Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2518-2529 (2014)
2000 – 2009
- 2008
- [j1]Masanari Nishimura, Nagisa Ishiura, Yoshiyuki Ishimori, Hiroyuki Kanbara, Hiroyuki Tomiyama:
High-Level Synthesis of Software Function Calls. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3556-3558 (2008)
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