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ORCIDA. M. Majid
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2010 – 2019
- 2013
[c9]David C. Keezer
, Carl Edward Gray, Te-Hui Chen, Ashraf Majid:
Practical methods for extending ATE to 40 and 50Gbps. ITC 2013: 1-10- 2011
- [c8]A. M. Majid, David C. Keezer:
Multi-function multi-GHz ATE extension using state-of-the-art FPGAs. ITC 2011: 1-10 - 2010
- [c7]A. M. Majid, David C. Keezer:
Stretching the limits of FPGA SerDes for enhanced ATE performance. DATE 2010: 202-207
2000 – 2009
- 2009
- [c6]David C. Keezer, Carl Gray, A. M. Majid, Dany Minier, Patrice Ducharme:
A development platform and electronic modules for automated test up to 20 Gbps. ITC 2009: 1-11 - 2008
- [c5]David C. Keezer, Dany Minier, Patrice Ducharme, A. M. Majid:
An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test. ITC 2008: 1-9 - 2007
- [i1]David C. Keezer, Carl Gray, Ashraf M. Majid, Nafeez Taher:
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. CoRR abs/0710.4761 (2007) - 2006
- [c4]A. M. Majid, David C. Keezer, Jayasanker Jayabalan, Mihai Rotaru:
Multi-Gigahertz Testing of Wafer-Level Packaged Devices. ITC 2006: 1-10 - 2005
- [c3]A. M. Majid, David C. Keezer, J. V. Karia:
A 5 Gbps Wafer-Level Tester. Asian Test Symposium 2005: 58-63 - [c2]David C. Keezer, Carl Gray, Ashraf M. Majid, Nafeez Taher:
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. DATE 2005: 152-157 - [c1]David C. Keezer, Carl Gray, Ashraf Majid, Nafeez Taher:
Implementing multi-gigahertz test systems using CMOS FPGAs and PECL components. ESSCIRC 2005: 291-294
Coauthor Index
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