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ORCIDDATE 2005: Munich, Germany
- 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. IEEE Computer Society 2005, ISBN 0-7695-2288-2
Volume 1
Keynote Addresses
- Jeong-Taek Kong:
SoC in Nanoera: Challenges and Endless Possibility. 2 - Garry Hughes:
Striking a New Balance in the Nanometer Era: First-Time-Right and Time-to-Market Demands Versus Technology Challenges. 3
1A: Partitioning and Optimisation for Reconfigurable Computing
- Nastaran Baradaran, Pedro C. Diniz:
A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures. 6-11 - Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi:
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization. 12-17 - Roman L. Lysecky, Frank Vahid:
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. 18-23 - Ray C. C. Cheung
, Wayne Luk, Peter Y. K. Cheung:
Reconfigurable Elliptic Curve Cryptosystems on a Chip. 24-29
Interactive Presentations
- Rui Rodrigues, João M. P. Cardoso:
An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs. 30-31 - N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin:
FPGA Architecture for Multi-Style Asynchronous Logic. 32-33
1B: Hot Topic - Analogue/Digital Circuit Design in 65nm: End of the Road
- Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich:
Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? 36-42
1C: SoC Design-for-Test
- Sandeep Kumar Goel, Erik Jan Marinissen:
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. 44-49 - Anuja Sehgal, Fang Liu, Sule Ozev, Krishnendu Chakrabarty:
Test Planning for Mixed-Signal SOCs with Wrapped Analog Cores. 50-55 - Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. 56-61
Interactive Presentation
- Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno:
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture. 62-63
1E: Embedded Tutorial - Cross-Pollination between HW and SW - Hard Lessons for Software, and Vice Versa
- Stephen A. Edwards:
The Challenges of Hardware Synthesis from C-Like Languages. 66-67 - Alexander G. Dean:
Software Thread Integration and Synthesis for Real-Time Applications. 68-69 - Ian Oliver:
Applying UML and MDA to Real Systems Design. 70-71
1F: Low Power Design with Error Tolerance
- Diana Marculescu:
Energy Bounds for Fault-Tolerant Nanoscale Designs. 74-79 - Himanshu Kaul, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge, Todd M. Austin:
DVS for On-Chip Bus Designs Based on Timing Error Correction. 80-85 - Le Cai, Yung-Hsiang Lu:
Joint Power Management of Memory and Disk. 86-91 - Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin:
Assertion-Based Design Exploration of DVS in Network Processor Architectures. 92-97
2A: Scheduling and Synthesis for Reconfigurable Computin
- Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis:
Instruction Scheduling for Dynamic Hardware Configurations. 100-105 - Javier Resano, Daniel Mozos, Francky Catthoor:
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware. 106-111 - Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers:
Optimized Generation of Data-Path from C Codes for FPGAs. 112-117
2B: Analogue Simulation, Placement and Statistical Analysis
- Ewout Martens, Georges G. E. Gielen:
Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series. 120-125 - Fang Liu, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev:
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing. 126-131 - Hratch Mangassarian, Mohab Anis:
On Statistical Timing Analysis with Inter- and Intra-Die Variations. 132-137 - Raoul F. Badaoui, Ranga Vemuri:
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis. 138-143
2C: Analogue and Gigahertz Test
- Koichiro Noguchi, Makoto Nagata:
On-Chip Multi-Channel Waveform Monitoring for Diagnostics of Mixed-Signal VLSI Circuits. 146-151 - David C. Keezer, Carl Gray, Ashraf M. Majid, Nafeez Taher:
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL. 152-157 - Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin:
Noise Figure Evaluation Using Low Cost BIST. 158-163 - Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi:
Specification Test Compaction for Analog Circuits and MEMS. 164-169
Interactive Presentations
- Rabeb Kheriji, V. Danelon, Jean-Louis Carbonéro, Salvador Mir:
Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach. 170-171 - Pekka Syri, Juha Häkkinen, Markku Moilanen:
IEEE 1149.4 Compatible ABMs for Basic RF Measurements. 172-173 - Carlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho:
Fault-Trajectory Approach for Fault Diagnosis on Analog Circuits. 174-175
2E: Ubiquitous Computing: Security and Energy Aspects
- Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring. 178-183 - Jung-Chun Kao, Radu Marculescu:
Energy-Aware Routing for E-Textile Applications. 184-189 - Arijit Ghosh, Tony Givargis:
LORD: A Localized, Reactive and Distributed Protocol for Node Scheduling in Wireless Sensor Networks. 190-195 - Bruno Bougard, Francky Catthoor, Denis C. Daly, Anantha P. Chandrakasan, Wim Dehaene:
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives. 196-201
Interactive Presentation
- Vivek Rai, Rabi N. Mahapatra:
Lifetime Modeling of a Sensor Network. 202-203
2F: Power Aware Design in DSM Technology
- José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura:
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. 206-211 - Hassan Hassan, Mohab Anis, Antoine El Daher, Mohamed I. Elmasry:
Activity Packing in FPGAs for Leakage Power Reduction. 212-217 - Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan:
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. 218-223 - Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy:
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. 224-229
Interactive Presentation
- Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Leakage-Aware Interconnect for On-Chip Network. 230-231
3A: Reconfigurability in MPSoC
- Vincent Nollet, Théodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet:
Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles. 234-239 - Austin Hung, William D. Bishop, Andrew A. Kennings:
Symmetric Multiprocessing on Programmable Chips Made Easy. 240-245 - Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor:
A Complete Network-On-Chip Emulation Framework. 246-251
Interactive Presentation
- Vincent Nollet, Prabhat Avasare, Jean-Yves Mignolet, Diederik Verkest:
Low Cost Task Migration Initiation in a Heterogeneous MP-SoC. 252-253 - Sander Stuijk, Twan Basten, Bart Mesman, Marc Geilen:
Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip. 254-255
3B: Analogue, Mixed-Signal and RF Circuits and Systems
- Paul Muller, Armin Tajalli, Seyed Mojtaba Atarodi, Yusuf Leblebici:
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit. 258-263 - Hua Tang, Ying Wei, Alex Doboli:
MINLP Based Topology Synthesis for Delta Sigma Modulators Optimized for Signal Path Complexity, Sensitivity and Power Consumption. 264-269 - Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay:
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. 270-275
Interactive Presentations
- Ludovic Barrandon, Samuel Crand, Dominique Houzet:
Systematic Figure of Merit Computation for the Design of Pipeline ADC. 277-278 - Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee:
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. 279-280
3C: Reliability at the Very Deep Sub-Micron Region
- Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes:
Accurate Reliability Evaluation and Enhancement via Probabilistic Transfer Matrices. 282-287 - Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee:
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits. 288-293 - Osama Neiroukh, Xiaoyu Song:
Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques. 294-299 - Jonathan R. Carter, Sule Ozev, Daniel J. Sorin:
Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown. 300-305
Interactive Presentations
- Ghazanfar Asadi, Mehdi Baradaran Tahoori:
An Accurate SER Estimation Method Based on Propagation Probability. 306-307 - Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes:
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. 308-309
3F: HW/SW Solutions for Low Power Multimedia Systems
- Arne Hamann, Rolf Ernst:
TDMA Time Slot and Turn Optimization with Evolutionary Search Techniques. 312-317 - Jennifer L. Wong, Weiping Liao, Fei Li, Lei He, Miodrag Potkonjak:
Scheduling of Soft Real-Time Systems for Context-Aware Applications. 318-323 - Fernando Rincón, Francisco Moya, Jesús Barba, Juan Carlos López:
Model Reuse through Hardware Design Patterns. 324-329 - Amr Talaat Abdel-Hamid, Sofiène Tahar, El Mostapha Aboulhamid:
A Public-Key Watermarking Technique for IP Designs. 330-335
Interactive Presentation
- Philippe Martin:
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer. 336-337
3F: HW/SW Solutions for Low Power Multimedia Systems
- Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha:
Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing. 340-345 - Ali Iranli, Hanif Fatemi, Massoud Pedram:
HEBS: Histogram Equalization for Backlight Scaling. 346-351 - Ümit Y. Ogras, Radu Marculescu:
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach. 352-357 - Tohru Ishihara, Farzan Fallah:
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. 358-363
4A: Embedded System Partitioning and Validation
- Benoît Miramond, Jean-Marc Delosme:
Design Space Exploration for Dynamically Reconfigurable Architectures. 366-371 - Arshad Jhumka, Stephan Klaus, Sorin A. Huss:
A Dependability-Driven System-Level Design Approach for Embedded Systems. 372-377 - Luciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe:
A Time Slice Based Scheduler Model for System Level Design. 378-383 - Jae-Gon Lee, Moo-Kyoung Chung, Ki-Yong Ahn, Sang-Heon Lee, Chong-Min Kyung:
A Prediction Packetizing Scheme for Reducing Channel Traffic in Transaction-Level Hardware/Software Co-Emulation. 384-389 - Ambar A. Gadkari, S. Ramesh:
Automated Synthesis of Assertion Monitors using Visual Specifications. 390-395
Interactive Presentation
- Greg Stitt, Frank Vahid:
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms. 396-397
4B: Logic Synthesis
- Aseem Agarwal, Kaviraj Chopra, David T. Blaauw:
Statistical Timing Based Optimization using Gate Sizing. 400-405 - Maxim Teslenko, Elena Dubrova:
An Efficient Algorithm for Finding Double-Vertex Dominators in Circuit Graphs. 406-411 - Alan Mishchenko, Robert K. Brayton:
SAT-Based Complete Don't-Care Computation for Network Optimization. 412-417 - Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations. 418-423 - G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain:
DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement. 424-429
Interactive Presentations
- Andrés Martinelli, Elena Dubrova:
Bound Set Selection and Circuit Re-Synthesis for Area/Delay Driven Decomposition. 430-431 - Igor L. Markov, Dmitri Maslov:
Uniformly-Switching Logic for Cryptographic Hardware. 432-433 - Guowu Yang, William N. N. Hung, Xiaoyu Song, Marek A. Perkowski:
Exact Synthesis of 3-Qubit Quantum Circuits from Non-Binary Quantum Gates Using Multiple-Valued Logic and Group Theory. 434-435
4C: Defect Detection and Characterisation
- Ananta K. Majhi, Mohamed Azimane, Guido Gronthoud, Maurice Lousberg, Stefan Eichenberger, Fred Bowen:
Memory Testing Under Different Stress Conditions: An Industrial Evaluation. 438-443 - Irith Pomeranz, Sudhakar M. Reddy:
Worst-Case and Average-Case Analysis of n-Detection Test Sets. 444-449 - Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz:
Defect Aware Test Patterns. 450-455 - Eric Liau, Doris Schmitt-Landsiedel:
Computational Intelligence Characterization Method of Semiconductor Device. 456-461
Interactive Presentations
- Laurent Lopez, Jean-Michel Portal, Didier Née:
A New Embedded Measurement Structure for eDRAM Capacitor. 462-463 - Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura:
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. 464-465
4E: Real-Time Scheduling
- Chuan-Yue Yang, Jian-Jia Chen, Tei-Wei Kuo:
An Approximation Algorithm for Energy-Efficient Scheduling on A Chip Multiprocessor. 468-473 - Haisang Wu, Binoy Ravindran, E. Douglas Jensen:
Energy-Efficient, Utility Accrual Real-Time Scheduling Under the Unimodal Arbitrary Arrival Model. 474-479 - Rafik Henia, Rolf Ernst:
Context-Aware Scheduling Analysis of Distributed Systems with Tree-Shaped Task-Dependencies. 480-485 - Samarjit Chakraborty, Lothar Thiele:
A New Task Model for Streaming Applications and Its Schedulability Analysis. 486-491 - Karsten Albers, Frank Slomka:
Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling. 492-497
Interactive Presentation
- He Hai, Zhong Yi-fang, Cai Chi-lan:
Unified Modeling of Complex Real-Time Control Systems. 498-499
4F: SoC Power Optimisation
- César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel:
Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. 502-507 - Mirko Loghi, Massimo Poncino:
Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions. 508-513 - Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi:
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints. 514-519 - Mirko Loghi, Paolo Azzoni, Massimo Poncino:
Tag Overflow Buffering: An Energy-Efficient Cache Architecture. 520-525
Interactive Presentations
- Min Li, Xiaobo Wu, Richard Yao, Xiaolang Yan:
Q-DPM: An Efficient Model-Free Dynamic Power Management Technique. 526-527 - Joel Coburn, Srivaths Ravi, Anand Raghunathan:
Hardware Accelerated Power Estimation. 528-529
4G: Embedded Tutorial - Platforms and Tools for Automotive System Design
- Alberto L. Sangiovanni-Vincentelli:
Integrated Electronics in the Car and the Design Chain Evolution or Revolution? 532-533 - Horst Brinkmeyer:
A New Approach to Component Testing. 534-535 - Thomas Illgen, Stefan Ortmann:
Process Oriented Software Quality Assurance - An Experience Report in Process Improvement - OEM Perspective. 536-537 - Joachim Langenwalter:
Embedded Automotive System Development Process. 538-539
5A: System Level Languages, Verification and Simulation
- Samar Abdi, Daniel D. Gajski:
Functional Validation of System Level Static Scheduling. 542-547 - Shuqing Zhao, Daniel D. Gajski:
Defining an Enhanced RTL Semantics. 548-553 - M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. 554-559 - Ali Habibi, Sofiène Tahar:
Design for Verification of SystemC Transaction Level Models. 560-565
Interactive Presentations
- Wolfgang Klingauf:
Systematic Transaction Level Modeling of Embedded Systems with SystemC. 566-567 - Sohini Dasgupta, Alexandre Yakovlev:
Modeling and Verification of Globally Asynchronous and Locally Synchronous Ring Architectures. 568-569
5B: Panel Session - Semiconductor Industry Disaggregation vs. Reaggregation: Who will be the Shark?
- Yervant Zorian, Bill Frerichs, Dennis Wassung, Jim Ensel, Guri Stark, Mike Gianfagna, Kamalesh N. Ruparel:
Semiconductor Industry Disaggregation vs Reaggregation: Who Will be the Shark? 572
5C: Reliable Memory Design
- Jin-Fu Li, Tsu-Wei Tseng, Chin-Long Wey:
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories. 574-579 - Luca Schiano, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli, Adelio Salsano:
On the Analysis of Reed Solomon Coding for Resilience to Transient/Permanent Faults in Highly Reliable Memories. 580-585