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Mun-Yang Park

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Journal Articles

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2013
[j3]
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  dblp key:
  - journals/iet-cds/ByunSHMPY13
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  persistent URL:
  - https://dblp.org/rec/journals/iet-cds/ByunSHMPY13
Sangjin Byun, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu:
1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector. IET Circuits Devices Syst. 7(3) (2013)
2012
[j2]
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  - journals/tcas/LeePMKPY12
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  - https://dblp.org/rec/journals/tcas/LeePMKPY12
Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu:
A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1706-1719 (2012)
2004
[j1]
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  - journals/jssc/KohPKY04
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  - https://dblp.org/rec/journals/jssc/KohPKY04
Kwang-Jin Koh, Mun-Yang Park, Cheon-Soo Kim, Hyun-Kyu Yu:
Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver. IEEE J. Solid State Circuits 39(6): 871-884 (2004)

Conference and Workshop Papers

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2004
[c1]
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  - conf/cicc/KimPPY04
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Young-Ho Kim, Jung-Woo Park, Mun-Yang Park, Hyun-Kyu Yu:
A 1.8V triode-type transconductor and its application to a 10MHz 3^rd-order Chebyshev low pass filter. CICC 2004: 53-56

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