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ORCIDVladislav Tartakovsky
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2020 – today
- 2021
[j2]Yosi Ben-Asher, Esti Stein
, Vladislav Tartakovsky:
FPGA Realization of the Reconfigurable Mesh Counting Algorithm. J. Circuits Syst. Comput. 30(9): 2150157:1-2150157:25 (2021)- 2020
- [b1]Vladislav Tartakovsky:
Speeding up the computations by using Non-Deterministic Branching programs instead of Boolean Cirquits. University of Haifa, Israel, 2020
2010 – 2019
- 2019
- [c6]Yosi Ben-Asher, Vladislav Tartakovsky:
Efficient Conversion of Boolean Circuits to Nondeterministic Branching Programs. IPDPS Workshops 2019: 655-662 - 2018
- [c5]Yosi Ben-Asher, Vladislav Tartakovsky, Katrina Portman, Orr Zilberman, Avishi Hadar:
An FPGA Scalable Parallel Viterbi Decoder. MCSoC 2018: 8-15 - 2017
- [j1]Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv:
Generating ASIPs with Reduced Number of Connections to the Register-File. Int. J. Parallel Program. 45(6): 1461-1487 (2017) - 2016
- [c4]Vladislav Tartakovsky:
Student Research Poster: Compiling Boolean Circuits to Non-deterministic Branching Programs to be Implemented by Light Switching Circuits. PACT 2016: 457 - 2015
- [c3]Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv:
Generating ASIPs with reduced number of connections to the register-file. SAMOS 2015: 238-245 - 2014
- [c2]Yosi Ben-Asher, Irina Lipov, Vladislav Tartakovsky, Dror Tiv:
Using Multi-op Instructions as a Way to Generate ASIPs with Optimized Pipeline Structure. FCCM 2014: 29 - 2012
- [c1]Yosi Ben-Asher, Eldar Fisher, Gadi Haber, Vladislav Tartakovsky:
Fast Evaluation of Boolean Circuits Based on Two-Players Game and Optical Connectivity Circuits. ICPP 2012: 21-29
Coauthor Index
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