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Mitsuo Nakamura

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Journal Articles

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2018
[j2]
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  - journals/ieicet/ShibataN18
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  - https://dblp.org/rec/journals/ieicet/ShibataN18
Nobutaro Shibata, Mitsuo Nakamura:
An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 101-A(8): 1185-1196 (2018)
2013
[j1]
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Mitsuo Nakamura, Mamoru Ugajin, Mitsuru Harada:
A 280-MHz CMOS Intra-Symbol Intermittent RF Front End for Adaptive Power Reduction of Wireless Receivers According to Received-Signal Intensity in Sensor Networks. IEICE Trans. Electron. 96-C(1): 93-101 (2013)

Conference and Workshop Papers

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2013
[c2]
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  - conf/mwscas/KishineIONKN13
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Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Hiroshi Koizumi, Mitsuo Nakamura:
Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS. MWSCAS 2013: 904-907
2012
[c1]
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Keiji Kishine, Hiromi Inaba, Yusuke Ohtomo, Makoto Nakamura, Mitsuo Nakamura:
Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. MWSCAS 2012: 602-605

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