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ORCIDBhupendra Singh Reniwal
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2020 – today
- 2024
[c11]Kavitha S, Binsu J. Kailath, Bhupendra Singh Reniwal:
CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural Networks. DATE 2024: 1-2- 2023
- [j6]Kavitha Soundrapandiyan
, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal:
Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 445-455 (2023) - [c10]Mohd Sakib Ansari S, Kavitha S, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application. VLSID 2023: 104-108 - [c9]Swetha Ananthanarayanan, Bhupendra Singh Reniwal, Abhishek Upadhyay:
Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing Approach. VLSID 2023: 109-114 - 2022
- [c8]S. Kavitha, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal:
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array. VDAT 2022: 262-274 - 2021
- [c7]Mythrai, Pragna, Kavitha S, P. Singh, A. P. Shah, S. K. Vishwakarma, Bhupendra Singh Reniwal:
Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation. VDAT 2021: 1-4
2010 – 2019
- 2019
- [j5]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, Devesh Dwivedi:
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. Circuits Syst. Signal Process. 38(4): 1482-1505 (2019) - [c6]Ankur Beohar, Gopal Raut, Gunjan Rajput, Abhinav Vishwakarma, Ambika Prasad Shah, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications. VDAT 2019: 655-663 - 2018
- [j4]Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma:
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. Integr. 62: 1-13 (2018) - 2017
- [j3]Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma:
Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications. J. Low Power Electron. 13(1): 47-59 (2017) - [j2]Bhupendra Singh Reniwal, Praneet Bhatia, Santosh Kumar Vishvakarma:
Design and investigation of variability aware sense amplifier for low power, high speed SRAM. Microelectron. J. 59: 22-32 (2017) - [c5]Bhupendra Singh Reniwal, P. Singh, Vikas Vijayvargiya, Santosh Kumar Vishvakarma:
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM. VLSID 2017: 335-340 - 2016
- [j1]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance. Circuits Syst. Signal Process. 35(9): 3066-3085 (2016) - 2015
- [c4]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET. ACM Great Lakes Symposium on VLSI 2015: 95-98 - [c3]Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal, V. Sharma, C. B. Khuswah, Devesh Dwivedi:
Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity. iNIS 2015: 29-34 - [c2]Praneet Bhatia, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
An offset-tolerant self-correcting sense amplifier for robust high speed SRAM. VDAT 2015: 1-6 - 2013
- [c1]Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM. VDAT 2013: 1-9
Coauthor Index
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