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ORCID24. ACM Great Lakes Symposium on VLSI 2015: Pittsburgh, PA, USA
- Alex K. Jones, Hai (Helen) Li, Ayse K. Coskun, Martin Margala:
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015. ACM 2015, ISBN 978-1-4503-3474-7
Keynote 1
- Krishnendu Chakrabarty:
Digital Microfluidic Biochips: Towards Functional Diversity, More than Moore, and Cyberphysical Integration. 1
Reliability, Resiliency, Robustness I
- Nima Aghaee, Zebo Peng, Petru Eles:
Efficient Test Application for Rapid Multi-Temperature Testing. 3-8 - Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini
, Maurice Herlihy, R. Iris Bahar:
Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution. 9-14 - Fatemeh Tehranipoor, Nima Karimian, Kan Xiao, John A. Chandy:
DRAM based Intrinsic Physical Unclonable Functions for System Level Security. 15-20 - Songwei Pei, Jingdong Zhang, Yu Jin, Song Jin, Jun Liu, Weizhi Xu:
An Effective TSV Self-Repair Scheme for 3D-Stacked ICs. 21-26
CAD for New Technologies
- Tiantao Lu, Ankur Srivastava:
Electromigration-aware Clock Tree Synthesis for TSV-based 3D-ICs. 27-32 - Tiansong Cui, Bowen Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram:
Layout Characterization and Power Density Analysis for Shorted-Gate and Independent-Gate 7nm FinFET Standard Cells. 33-38 - Sandeep Miryala, Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino, Luca Gaetano Amarù, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. 39-44 - Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky:
A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits. 45-50
Best Paper Session
- Linbin Chen, Jie Han, Weiqiang Liu, Fabrizio Lombardi:
Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing. 51-56 - Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic:
Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models. 57-62 - Sai Vineel Reddy Chittamuru, Srinivas Desai, Sudeep Pasricha:
Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures. 63-68 - Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia:
A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. 69-74
Poster Session 1
- Yukai Chen, Andrea Calimera, Enrico Macii, Massimo Poncino:
Characterizing the Activity Factor in NBTI Aging Models for Embedded Cores. 75-78 - Yue Ma, Thidapat Chantem, Xiaobo Sharon Hu, Robert P. Dick:
Improving Lifetime of Multicore Soft Real-Time Systems through Global Utilization Control. 79-82 - Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, David Z. Pan, Moshe Preil, Azat Latypov:
Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design. 83-86 - Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, Pierre-Olivier Ribet:
Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. 87-90 - Fabrizio Lombardi, Wei Wei, Kazuteru Namba:
Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits. 91-94 - Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET. 95-98 - Ibtissem Seghaier, Mohamed H. Zaki, Sofiène Tahar:
Statistically Validating the Impact of Process Variations on Analog and Mixed Signal Designs. 99-102 - Dilip P. Vasudevan, Andrew A. Chien:
The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data. 103-106 - Bo Yuan, Keshab K. Parhi:
Reduced-latency LLR-based SC List Decoder for Polar Codes. 107-110 - Monther Abusultan, Sunil P. Khatri:
Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs. 111-114
Energy Efficient Systems
- Tosiron Adegbija, Ann Gordon-Ross:
Phase-based Cache Locking for Embedded Systems. 115-120 - Dharanidhar Dang, Biplab Patra, Rabi N. Mahapatra:
A Multilayered Design Approach for Efficient Hybrid 3D Photonics Network-on-chip. 121-126 - Alireza Shafaei Bejestan, Yanzhi Wang, Srikanth Ramadurgam, Yuankun Xue, Paul Bogdan, Massoud Pedram:
Analyzing the Dark Silicon Phenomenon in a Many-Core Chip Multi-Processor under Deeply-Scaled Process Technologies. 127-132
Interconnects and NoCs
- Sourav Das, Dongjin Lee, Dae Hyun Kim, Partha Pratim Pande:
Small-World Network Enabled Energy Efficient and Robust 3D NoC Architectures. 133-138 - Alexandre Briere, Julien Denoulet, Andréa Pinna, Bertrand Granado, François Pêcheux, Eren Unlu, Yves Louët, Christophe Moy:
A Dynamically Reconfigurable RF NoC for Many-Core. 139-144
Keynote II
- Erik Brunvand:
Computational Thinking Meets Design Thinking: Technology and Arts Collaborations. 145
Keynote III
- Zhenqiang Jack Ma:
Graphene Neural Sensors for Next Generation In Vivo Imaging and Optogenetics. 147
Reliability, Resiliency, Robustness II
- Amir Yazdanbakhsh, David J. Palframan, Azadeh Davoodi, Nam Sung Kim, Mikko H. Lipasti:
Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors. 149-154 - Mehdi Sadi, Mark Tehranipoor, Xiaoxiao Wang, LeRoy Winemberg:
Speed Binning Using Machine Learning And On-chip Slack Sensors. 155-160 - Michail Mavropoulos, Georgios Keramidas, Grigorios Adamopoulos, Dimitris Nikolos:
Reconfigurable: Self Adaptive Fault Tolerant Cache Memory for DVS enabled Systems. 161-166
VLSI Design
- Anirban Sengupta, Saumya Bhadauria:
Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis. 167-172 - Samira Ataei, James E. Stine:
Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers. 173-178 - Donald Kline Jr., Kai Wang, Rami G. Melhem, Alex K. Jones:
MSCS: Multi-hop Segmented Circuit Switching. 179-184
Special Session: Neuromorphic Computing based on Resistive Devices
- Beiye Liu, Wei Wen, Yiran Chen, Xin Li, Chi-Ruo Wu, Tsung-Yi Ho:
EDA Challenges for Memristor-Crossbar based Neuromorphic Computing. 185-188 - Yu Wang, Tianqi Tang, Lixue Xia, Boxun Li, Peng Gu, Huazhong Yang, Hai Li, Yuan Xie:
Energy Efficient RRAM Spiking Neural Network for Real Time Classification. 189-194 - Shimeng Yu, Yu Cao:
On-chip Sparse Learning with Resistive Cross-point Array Architecture. 195-197
Special Session: Advances in Neuromorphic Architectures and Future Applications
- Lukas Cavigelli, David Gschwend, Christoph Mayer, Samuel Willi, Beat Muheim, Luca Benini:
Origami: A Convolutional Network Accelerator. 199-204 - Robin Danilo, Philippe Coussy, Laura Conde-Canencia, Vincent Gripon, Warren J. Gross:
Restricted Clustered Neural Network for Storing Real Data. 205-210 - Michel Paindavoine, Olivier Boisard, Alexandre Carbon, Jean-Marc Philippe, Olivier Brousse:
NeuroDSP Accelerator for Face Detection Application. 211-215
Poster Session 2
- Yong Li, Haifeng Xu, Rami G. Melhem, Alex K. Jones:
Space Oblivious Compression: Power Reduction for Non-Volatile Main Memories. 217-220 - Poovaiah M. Palangappa, Kartik Mohanram:
Flip-Mirror-Rotate: An Architecture for Bit-write Reduction and Wear Leveling in Non-volatile Memories. 221-224 - Joonho Kong, Arslan Munir, Farinaz Koushanfar:
Fine-Grained Voltage Boosting for Improving Yield in Near-Threshold Many-Core Processors. 225-228 - Georgios Zervakis, Kostas Tsoumanis, Sotirios Xydis, Nicholas Axelos, Kiamal Z. Pekmestzi:
Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis. 229-232 - Rosario Distefano, Franco Fummi, Carlo Laudanna, Nicola Bombieri, Rosalba Giugno:
A SystemC Platform for Signal Transduction Modelling and Simulation in Systems Biology. 233-236 - Seyyed Hasan Mozafari, Brett H. Meyer, Kevin Skadron:
Yield-aware Performance-Cost Characterization for Multi-Core SIMT. 237-240 - Luke Murray, Sunil P. Khatri:
An Efficient Approach to Sample On-Chip Power Supplies. 241-244 - Thomas Marconi, Sorin Cotofana:
Dynamic Bitstream Length Scaling Energy Effective Stochastic LDPC Decoding. 245-248 - Brian Neel, Matthew Kennedy, Avinash Karanth Kodi:
Dynamic Power Reduction Techniques in On-Chip Photonic Interconnects. 249-252
Emerging Technologies
- Roberto Giorgio Rizzo, Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino:
Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. 253-258 - Pilin Junsangsri, Fabrizio Lombardi, Jie Han:
A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM). 259-264 - K. M. Mohsin, Ashok Srivastava:
Characterization of SWCNT Bundle Based VLSI Interconnect with Self-heating Induced Scatterings. 265-270 - Yandan Wang, Wei Wen, Hai Li, Miao Hu:
A Novel True Random Number Generator Design Leveraging Emerging Memristor Technology. 271-276 - Qiuwen Lou, Indranil Palit, András Horváth, Xiaobo Sharon Hu, Michael T. Niemier, Joseph Nahas:
TFET-based Operational Transconductance Amplifier Design for CNN Systems. 277-282
CAD and Circuits I
- Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks. 283-288 - Wei Ye, Bei Yu, David Z. Pan, Yongchan Ban, Lars Liebmann:
Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line. 289-294 - Hafiz ul Asad, Kevin D. Jones:
Inevitability of Phase-locking in a Charge Pump Phase Lock Loop using Deductive Verification. 295-300 - Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin:
A Novel Static D-Flip-Flop Topology for Low Swing Clocking. 301-306 - Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev:
Voltage-Boosted Synchronizers. 307-312
Keynote IV
- Andrew Schwartz:
Recent Advances in Brain-controlled Prosthetics for Paralysis: Friday Keynote. 313
Special Session: Bio Design Automation
- Qinsi Wang, Natasa Miskov-Zivanov, Cheryl Telmer, Edmund M. Clarke:
Formal Analysis Provides Parameters for Guiding Hyperoxidation in Bacteria using Phototoxic Proteins. 315-320 - Devin P. Sullivan, Rohan Arepally, Robert F. Murphy, José Juan Tapia, James R. Faeder, Markus Dittrich, Jacob Czech:
Design Automation for Biological Models: A Pipeline that Incorporates Spatial and Molecular Complexity. 321-323 - Jason Lohmueller:
Mammalian Synthetic Gene Networks. 325-326 - Natasa Miskov-Zivanov:
Automation of Biological Model Learning, Design and Analysis. 327-329
Special Session: Emerging Computing Paradigm for Error-Tolerant Applications: Approximate Computing and Stochastic Computing
- Armin Alaghi, John P. Hayes:
On the Functions Realized by Stochastic Computing Circuits. 331-336 - Ye Tian, Qian Zhang, Ting Wang, Feng Yuan, Qiang Xu:
ApproxMA: Approximate Memory Access for Dynamic Precision Scaling. 337-342 - Honglan Jiang, Jie Han, Fabrizio Lombardi:
A Comparative Review and Evaluation of Approximate Adders. 343-348 - Yi Wu, Chen Wang, Weikang Qian:
Minimizing Error of Stochastic Computation through Linear Transformation. 349-354
CAD and Circuits II
- Robert Najvirt, Ulrich Schmid, Michael Hofbauer, Matthias Függer, Thomas Nowak, Kurt Schweiger:
Experimental Validation of a Faithful Binary Circuit Model. 355-360 - Jiani Xie, C. Y. Roger Chen:
Lookup Table Based Discrete Gate Sizing for Delay Minimization with Modified Elmore Delay Model. 361-366 - Mineo Kaneko:
A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling. 367-372
Power and Temperature-Aware Design
- Ali Akbari, Saadat Pour-Mozafari, Hamid Noori, Farhad Mehdipour:
Dynamic Task Priority Scaling for Thermal Management of Multi-core Processors with Heavy Workload. 373-378 - Shiting (Justin) Lu, Russell Tessier, Wayne P. Burleson:
Reinforcement Learning for Thermal-aware Many-core Task Allocation. 379-384 - Katayoun Neshatpour, Houman Homayoun, Amin Khajeh, Wayne P. Burleson:
Revisiting Dynamic Thermal Management Exploiting Inverse Thermal Dependence. 385-390 - Mohammad Hossein Hajkazemi, Michael Chorney, Reyhaneh Jabbarvand Behrouz, Mohammad Khavari Tavana, Houman Homayoun:
Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory. 391-396 - Avijit Chakraborty, D. M. H. Walker:
Optimizing VMIN of ROM Arrays Without Loss of Noise Margin. 397-402
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