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Nattha Sretasereekul
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2000 – 2009
- 2003
- [j2]Nattha Sretasereekul, Takashi Nanya:
Eliminating Isochronic-Fork Constraints in Quasi-Delay-Insensitive Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(4): 900-907 (2003) - [j1]Nattha Sretasereekul, Hiroshi Saito, Euiseok Kim, Metehan Özcan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3028-3037 (2003) - [c4]Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC 2003: 184-195 - [c3]Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya:
A zero-time-overhead asynchronous four-phase controller. ISCAS (5) 2003: 205-208 - [c2]Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya:
Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) 2003: 617-620 - 2001
- [c1]Nattha Sretasereekul, Takashi Nanya:
Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. ASP-DAC 2001: 437-442
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