default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISCAS 2003: Bangkok, Thailand - Volume 5
- Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003. IEEE 2003, ISBN 0-7803-7761-3
- Michael W. Baker, Serhii M. Zhak, Rahul Sarpeshkar:
A micropower envelope detector for audio applications. 1-4 - Rizwan Bashirullah, Wentai Liu, Ying Ji, Gurhan Alper Kendir, Mohanasankar Sivaprakasam, Guoxing Wang, B. Pundi:
A smart bi-directional telemetry unit for retinal prosthetic device. 5-8 - Alexander Frey, Martin Jenkner, Meinrad Schienle, Christian Paulus, Birgit Holzapfl, Petra Schindler-Bauer, Franz Hofmann, Dirk Kuhlmeier, Jürgen Krause, Jörg Albers, Walter Gumbrecht, Doris Schmitt-Landsiedel, Roland Thewes:
Design of an integrated potentiostat circuit for CMOS bio sensor chips. 9-12 - G. Mulliken, Mihir Naware, A. Bandyopadhyay, Gert Cauwenberghs, Nitish V. Thakor
:
Distributed neurochemical sensing: in vitro experiments. 13-16 - Marek R. Ogiela, Ryszard Tadeusiewicz:
Visual signal processing and image understanding in biomedical systems. 17-20 - Thitiporn Chanwimaluang, Guoliang Fan:
An efficient blood vessel detection algorithm for retinal images using local entropy thresholding. 21-24 - Paul Dan Cristea:
Phase analysis of DNA genomic signals. 25-28 - Hamid Hassanpour, Mostefa Mesbah, Boualem Boashash:
Enhanced time-frequency features for neonatal EEG seizure detection. 29-32 - Pega Zarjam, Mostefa Mesbah, Boualem Boashash:
An optimal feature set for seizure detection systems for newborn EEG signals. 33-36 - Sandro A. P. Haddad, Sebastian Gieltjes, Richard Houben, Wouter A. Serdijn:
An ultra low-power dynamic translinear cardiac sense amplifier for pacemakers. 37-40 - Timothy Kuan-Ta Lu, Michael W. Baker, Christopher D. Salthouse, Ji-Jon Sit, Serhii M. Zhak, Rahul Sarpeshkar:
A micropower analog VLSI processing channel for bionic ears and speech-recognition front ends. 41-44 - Maysam Ghovanloo, Khalil Najafi:
A high-rate frequency shift keying demodulator chip for wireless biomedical implants. 45-48 - Andrea Gerosa, Andrea Neviani:
A very low-power 8-bit Sigma-Delta converter in a 0.8µm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8 V. 49-52 - Jonathan Coulombe, Jean-François Gervais, Mohamad Sawan:
A cortical stimulator with monitoring capabilities using a novel 1 Mbps ASK data link. 53-56 - Shuenn-Yuh Lee, Shyh-Chyang Lee, Jia-Jin Jason Chen:
VLSI implementation of wireless bi-directional communication circuits for micro-stimulator. 57-60 - Okundu C. Omeni, Chris Toumazou:
A CMOS micro-power wideband data/power transfer system for biomedical implants. 61-64 - Karn Opasjumruskit, Naiyavudhi Wongkomet:
A CMOS current-to-LCD interface for portable amperometric sensing systems. 65-68 - Christian Panis, Raimund Leitner, Herbert Grünbacher, Jari Nurmi:
xLIW - a scaleable long instruction word. 69-72 - H. S. Ng, Sui-Tung Mak, Kai-Pui Lam:
Field programmable gate arrays and analog implementation of BRIN for optimization problems. 73-76 - Kamran Farzan, David A. Johns:
A low-complexity power-efficient signaling scheme for chip-to-chip communication. 77-80 - Robert Siegmund, Dietmar Müller:
Efficient modeling and synthesis of on-chip communication protocols for network-on-chip design. 81-84 - Marcus van Ierssel, Tooraj Esmailian, Ali Sheikholeslami, P. S. Pasupathy:
Signaling capacity of FR4 PCB traces for chip-to-chip communication. 85-88 - Kuo-Hsing Cheng, Chung-Yu Chang, Chia-Hung Wei:
A CMOS charge pump for sub-2.0 V operation. 89-92 - Nam-Seog Kim, Yong-Jin Yoon, Uk-Rae Cho, Hyun-Geun Byun:
New dynamic logic-level converters for high performance application. 93-96 - Ming-Dou Ker, Chia-Sheng Tsai:
Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit. 97-100 - Sang-Chul Moon, In-Cheol Park:
Area-efficient memory-based architecture for FFT processing. 101-104 - Hoseok Chang, Wonchul Lee, Wonyong Sung:
Optimization of power consumption for an ARM7-based multimedia handheld device. 105-108 - Zili Shao, Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai:
Loop scheduling for minimizing schedule length and switching activities. 109-112 - Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner:
Variable delay ripple carry adder with carry chain interrupt detection. 113-116 - Jos Sulistyo, Dong Sam Ha:
5 GHz pipelined multiplier and MAC in 0.18µm complementary static CMOS. 117-120 - Hwang-Cherng Chow, I-Chyn Wey:
A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder. 121-124 - Siew Kei Lam, Devendra K. Chaudhaiy, Thambipillai Srikanthan:
Low cost logarithmic techniques for high-precision computations. 125-128 - Dimitrios Soudris, K. Sgouropoulos, Konstantinos Tatas, Vasilis F. Pavlidis, Adonios Thanailakis:
A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems. 129-132 - Andrea Lodi, Carlo Chiesa, Fabio Campi, Mario Toma:
A flexible LUT-based carry chain for FPGAs. 133-136 - K. J. Cho, E. M. Choi, Jin-Gyun Chung, M. S. Lim, J. W. Kim:
Low-error fixed-width squarer design. 137-140 - Aamir A. Farooqui, Vojin G. Oklobdzija, Sadiq M. Sait:
Area-time optimal adder with relative placement generator. 141-144 - Guido Bertoni, A. Bircan, Luca Breveglieri, Pasqualina Fragneto, Marco Macchetti, Vittorio Zaccaria:
About the performances of the Advanced Encryption Standard in embedded systems with cache memory. 145-148 - Junhyung Um, Sangwoo Lee, Youngsoo Park, Sungik Jun, Taewhan Kim:
An efficient inverse multiplier/divider architecture for cryptography systems. 149-152 - Nicolas Sklavos, Odysseas G. Koufopavlou:
On the hardware implementations of the SHA-2 (256, 384, 512) hash functions. 153-156 - Wonjong Kim, Seungchul Kim, Hanjin Cho, Kwang-youb Lee:
A fast-serial finite field multiplier without increasing the number of registers. 157-160 - Kay-Chuan Benny Tan, Tughrul Arslan:
Shift-accumulator ALU centric JPEG2000 5/3 lifting based discrete wavelet transform architecture. 161-164 - Harri Lampinen, Pauli Perälä, Olli Vainio:
Design of a self-timed asynchronous parallel FIR filter using CSCD. 165-168 - Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III:
Accurate delay model and experimental verification for current/voltage mode on-chip interconnects. 169-172 - Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen:
Area-effective FIR filter design for multiplier-less implementation. 173-176 - I. M. Hyjazie, Chunyan Wang:
An approach for improving the speed of content addressable memories. 177-180 - Yu-Cheng Fan, Hen-Wai Tsao:
Watermarking based IP core protection. 181-184 - Seong-Il Park, In-Cheol Park:
History-based memory mode prediction for improving memory performance. 185-188 - Mutlu Avci, Tülay Yildirim:
A coding method for 123 decision diagram pass transistor logic circuit synthesis. 189-192 - Yngvar Berg, Snorre Aunet, Omid Mirmotahari, Mats Høvin:
Novel recharge semi-floating-gate CMOS logic for multiple-valued systems. 193-196 - Xiao Yan Yu, Vojin G. Oklobdzija, William W. Walker:
An efficient transistor optimizer for custom circuits. 197-200 - Naofumi Homma, Takafumi Aoki, Makoto Motegi, Tatsuo Higuchi:
A framework of evolutionary graph generation system and its application to circuit synthesis. 201-204 - Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya:
A zero-time-overhead asynchronous four-phase controller. 205-208 - Kuo-Hsing Cheng, Yang-Han Lee, Wei-Chun Chang:
A new robust handshake for asymmetric asynchronous micro-pipelines. 209-212 - Reza Sedaghat:
A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation. 213-216 - Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh:
Design of a switch for network on chip applications. 217-220 - Shugang Wei, Kensuke Shimizu:
Modulo (2p ± 1) multipliers using a three-operand modular addition and Booth recoding based on signed-digit number arithmetic. 221-224 - Giorgos Dimitrakopoulos, Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
A systematic methodology for designing area-time efficient parallel-prefix modulo 2n - 1 adders. 225-228 - Ioannis Kouretas, Vassilis Paliouras:
High-radix redundant circuits for RNS modulo rn-1, rn, or rn+1. 229-232 - Peter Celinski, Derek Abbott, Sorin Dan Cotofana:
Area efficient, high speed parallel counter circuits using charge recycling threshold logic. 233-236 - Giorgos Dimitrakopoulos, Xrysovalantis Kavousianos, Dimitris Nikolos:
Virtual-scan: a novel approach for software-based self-testing of microprocessors. 237-240 - Sanghoon Choi, William R. Eisenstadt, Robert M. Fox:
Design of programmable embedded IF source for design self-test. 241-244 - Daniel Große, Rolf Drechsler:
Formal verification of LTL formulas for SystemC designs. 245-248 - Ansuman Banerjee, Pallab Dasgupta, Partha Pratim Chakrabarti:
Open computation tree logic with fairness. 249-252 - Marius Padure, Sorin Cotofana, Stamatis Vassiliadis:
Design and experimental results of a CMOS flip-flop featuring embedded threshold logic. 253-256 - Sang-Dae Shin, Hun Choi, Bai-Sun Kong:
Variable sampling window flip-flop for low-power application. 257-260 - Massimo Alioto, Gaetano Palumbo:
Design of MUX, XOR and D-latch SCL gates. 261-264 - Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou:
Parameterized and low power DSP core for embedded systems. 265-268 - Shrutin Ulman:
Macromodel for short circuit power dissipation of submicron CMOS inverters and its application to design CMOS buffers. 269-272 - Magdy A. El-Moursy, Eby G. Friedman:
Inductive interconnect width optimization for low power. 273-276 - Edwin Naroska, Shanq-Jang Ruan, Feipei Lai, Uwe Schwiegelshohn, Le-Chin Liu:
On optimizing power and crosstalk for bus coupling capacitance using genetic algorithms. 277-280 - D. S. Hong, Mourad N. El-Gamal:
Low operating voltage and short settling time CMOS charge pump for MEMS applications. 281-284 - Louie Pylarinos, Khoman Phang:
Analysis of output ripple in multi-phase clocked charge pumps. 285-288 - Ali Abbasian, S. H. Rasouli, Ali Afzali-Kusha, Mehrdad Nourani:
No-race charge recycling complementary pass transistor logic (NCRCPL) for low power applications. 289-292 - Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin:
A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. 293-296 - Hojun Kim, Jin-Gyun Chung:
Minimizing switching activity in input word by offset and its low power applications for FIR filters. 297-300 - Kuang-Fu Cheng, Sau-Gee Chen:
A low-complexity correlation algorithm. 301-304 - Pedro Julián, Andreas G. Andreou, Pablo Sergio Mandolesi, David H. Goldberg:
A low-power CMOS integrated circuit for bearing estimation. 305-308 - Lap-Fai Leung, Chi-Ying Tsui, Wing-Hung Ki:
Simultaneous task allocation, scheduling and voltage assignment for multiple-processors-core systems using mixed integer nonlinear programming. 309-312 - Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. 313-316 - Mingyan Zhang, Jiangmin Gu, Chip-Hong Chang:
A novel hybrid pass logic with static CMOS output drive full-adder cell. 317-320 - Jiangmin Gu, Chip-Hong Chang:
Ultra low voltage, low power 4-2 compressor for high speed multiplications. 321-324 - Asim J. Al-Khalili, Aiping Hu:
Design of a 32-bit squarer - exploiting addition redundancy. 325-328 - Yinshui Xia, B. Ali, A. E. A. Almaini:
Area and power optimization of FPRM function based circuits. 329-332 - Anders Berkeman, Viktor Öwall:
A configurable divider using digit recurrence. 333-336 - Pak-Keung Leung, Chiu-sing Choy, Cheong-Fat Chan, Kong-Pang Pun:
A low power asynchronous GF(2173) ALU for elliptic curve crypto-processor. 337-340 - Ahmet T. Erdogan, Tughrul Arslan:
Low power block based FIR filtering cores. 341-344 - Masayoshi Fujino, Vasily G. Moshnyaga:
Dynamic operand transformation for low-power multiplier-accumulator design. 345-348 - Vinita V. Deodhar, Jeffrey A. Davis:
Voltage scaling and repeater insertion for high-throughput low-power interconnects. 349-352 - Mohd. Hasan, Tughrul Arslan:
A triple port RAM based low power commutator architecture for a pipelined FFT processor. 353-356 - Richard C. S. Morling, Izzet Kale, S. J. Morris, F. Custode:
DSP engine for ultra-low-power audio applications. 357-360 - Sunan Tugsinavisut, Suwicha Jirayucharoensak, Peter A. Beerel:
An asynchronous pipeline comparisons with application to DCT matrix-vector multiplication. 361-364 - Shao-Sheng Yang, Pao-Lin Guo, Tsin-Yuan Chang, Jin-Hua Hong:
A multi-phase charge-sharing technique without external capacitor for low-power TFT-LCD column drivers. 365-368 - Jader A. De Lima:
An active leakage-injection scheme applied to low-voltage SRAMs. 369-372 - Chi-Sheng Lin, Kuan-Hua Chen, Bin-Da Liu:
Low-power and low-voltage fully parallel content-addressable memory. 373-376 - Byung-Do Yang, Lee-Sup Kim:
A low power charge sharing ROM using dummy bit lines. 377-380 - Chien-Chung Chua, Bah-Hwee Gwee, Joseph Sylvester Chang:
A low-voltage micropower asynchronous multiplier for a multiplierless FIR filter. 381-384 - Alberto Macii, Enrico Macii, Massimo Poncino:
Increasing the locality of memory access patterns by low-overhead hardware address relocation. 385-388 - Chunhong Chen, Jiang Zhao, Majid Ahmadi:
A semi-Gray encoding algorithm for low-power state assignment. 389-392 - Marek Wróblewski, Matthias Müller, Andreas Wortmann, Sven Simon, Wilhelm Pieper, Josef A. Nossek:
A power efficient register file architecture using master latch sharing. 393-396 - Sei Hyung Jang:
A new synchronous mirror delay with an auto-skew-generation circuit. 397-400 - Olivier Thomas, Amara Amara:
An SOI 4 transistors self-refresh ultra-low-voltage memory cell. 401-404 - Hing-mo Lam, Chi-Ying Tsui:
High performance and low power completion detection circuit. 405-408 - Toshifumi Enomoto, Tomohito Ei:
Low-power CMOS circuit techniques for motion estimators. 409-412 - Alberto Nannarelli, Gian Carlo Cardarilli, Marco Re:
Power-delay tradeoffs in residue number system. 413-416 - Eleftheria Athanasopoulou, Christoforos N. Hadjicostis:
Upper and lower bounds on FSM switching activity. 417-420 - Luigi Carro, Edgard de Faria Corrêa, R. Cardozo, Fernando Moraes, Sergio Bampi:
Exploiting reconfigurability for low-power control of embedded processors. 421-424 - Kuo-Hsing Cheng, Yung-Hsiang Lin:
A dual-pulse-clock double edge triggered flip-flop for low voltage and high speed application. 425-428 - Mircea R. Stan, Marco Barcella:
MTCMOS with outer feedback (MTOF) flip-flops. 429-432 - Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Comparison of synthesized bus and crossbar interconnection architectures. 433-436 - Thomas Olsson, Peter Nilsson:
A digitally controlled PLL for digital SOCs. 437-440 - P. C. Chen, James B. Kuo:
Novel sub-1V CMOS domino dynamic logic circuit using a direct bootstrap (DB) technique for low-voltage CMOS VLSI. 441-444 - Su Kio, Kian Haur Chong, Carl Sechen:
A low power delayed-clocks generation and distribution system. 445-448 - Faisal A. Musa, Anthony Chan Carusone:
Clock recovery in high-speed multilevel serial links. 449-452 - Turan Demirci, Ilhan Hatirnaz, Yusuf Leblebici:
Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity. 453-456 - Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji:
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning. 457-460 - Renato Fernandes Hentschke, Ricardo Reis:
Plic-Plac: a novel constructive algorithm for placement. 461-464 - Niwat Waropus, Rajendar Koltur, Malgorzata Chrzanowska-Jeske:
Graph-based approach to evaluate net routability of a floorplan. 465-468 - Michael A. Soderstrand:
CSD multipliers for FPGA DSP applications. 469-472 - Andrey V. Mezhiba, Eby G. Friedman:
Electrical characteristics of multi-layer power distribution grids. 473-476 - Noha H. Mahmoud, Yehea I. Ismail:
Accurate rise time and overshoots estimation in RLC interconnects. 477-480 - Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi:
Noise-constrained interconnect optimization for nanometer technologies. 481-484 - Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
A crosstalk aware two-pin net router. 485-488 - Sarat C. Maruvada, Karthik Krishnamoorthy, Subodh Annojvala, Florin Balasa:
Placement with symmetry constraints for analog layout using red-black trees. 489-492 - Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu:
Arbitrary convex and concave rectilinear block packing based on corner block list. 493-496 - Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji:
General iterative heuristics for VLSI multiobjective partitioning. 497-500 - Jyh Perng Fang, Sao-Jie Chen:
Tile-graph-based power planning. 501-504 - Eun-Gu Jung, Byung-Soo Choi, Dong-Ik Lee:
High performance asynchronous bus for SoC. 505-508 - Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen:
Minimizing coupling jitter by buffer resizing for coupled clock networks. 509-512 - Kenichi Okada, Kento Yamaoka, Hidetoshi Onodera:
Statistical modeling of gate-delay variation with consideration of intra-gate variability. 513-516 - Mohammad M. Mansour, Amit Mehrotra:
Efficient core designs based on parameterized macrocells with accurate delay models. 517-520 - Chien-In Henry Chen, Kiran George:
Configurable two-dimensional linear feedback shifter registers for deterministic and random patterns [logic BIST]. 521-524 - Dun Zhao, Shambhu Upudhyaya:
A resource balancing approach to SoC test scheduling. 525-528 - Christoforos N. Hadjicostis:
Aliasing probability calculations in nonlinear compactors. 529-532 - Beatriz Olleta, Lance Juffer, Degang Chen, Randall L. Geiger:
A deterministic dynamic element matching approach to ADC testing. 533-536 - Kumar L. Parthasarathy, Le Jin, Turker Kuyel, Dana Price, Degang Chen, Randall L. Geiger:
Experimental evaluation and validation of a BIST algorithm for characterization of A/D converter performance. 537-540 - Mohammad H. Tehranipour, Mehrdad Nourani, Seid Mehdi Fakhraie, Ali Afzali-Kusha:
Systematic test program generation for SoC testing using embedded processor. 541-544 - Aiman H. El-Maleh, Khaled Al-Utaibi:
On efficient extraction of partially specified test sets for synchronous sequential circuits. 545-548 - Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang:
Combinational circuit fault diagnosis using logic emulation. 549-552 - Meng Lieh Sheu, Tai Ping Sun, Chi Wen Lu, Mon Chau Shie:
The fault detection of cross-check test scheme for infrared FPA. 553-556 - Alfio Zanchi, Ioannis Papantonopoulos, Frank (Ching-Yuh) Tsay:
Measurement and SPICE prediction of sub-picosecond clock jitter in A/D converters. 557-560 - Rashid Rashidzadeh, Majid Ahmadi, William C. Miller:
A tester-on-chip implementation in 0.18µ CMOS utilizing a MEMS interface. 561-564 - Klaus D. Maier:
On-chip debug support for embedded Systems-on-Chip. 565-568 - Massimo Conti, Paolo Crippa, Francesco Fedecostunte, Simone Orcioni, F. Ricciardi, Claudio Turchetti, Loris Vendrame:
A modular test structure for CMOS mismatch characterization. 569-572 - Dimitris G. Nikolos, Dimitris Nikolos, Haridimos T. Vergos, Costas Efstathiou:
Efficient BIST schemes for RNS datapaths. 573-576 - Kuo-Hsing Cheng, Shu-Yu Jiang, Zong-Shen Chen:
BIST for clock jitter measurements. 577-580 - Kaamran Raahemifar, Majid Ahmadi:
A new initialization technique for asynchronous circuits. 581-584 - Meigen Shen, Li-Rong Zheng, Hannu Tenhunen:
Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip. 585-588 - Sébastien Bilavarn, Guy Gogniat, Jean Luc Philippe, Lilian Bossuet:
Fast prototyping of reconfigurable architectures from a C program. 589-592 - Issam Maalej, Guy Gogniat, Mohamed Abid, Jean Luc Philippe:
Interface design approach for system on chip based on configuration. 593-596 - Karen O. Egiazarian, Jaakko Astola, Radomir S. Stankovic, Milena Stankovic:
Circuit design from optimal wavelet packet series expressions. 597-600 - Qingfeng Zhuge, Edwin Hsing-Mean Sha, Chantana Chantrapornchai:
An Integrated Framework of Design Optimization and Space Minimization for DSP applications. 601-604 - Rüdiger Ebendt:
Reducing the number of variable movements in exact BDD minimization. 605-608 - Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir:
A novel improvement technique for high-level test synthesis. 609-612 - Vassilis Androutsopoulos, T. J. W. Clarke, Mike Brookes:
Synthesis and optimization of interfaces between hardware modules with incompatible protocols. 613-616 - Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya:
Control signal sharing of asynchronous circuits using datapath delay information. 617-620 - Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk:
Multitasking in hardware-software codesign for reconfigurable computer. 621-624 - Byoung-Woon Kim, Chong-Min Kyung:
System-on-Chip design using intellectual properties with imprecise design costs. 625-628 - Nattawut Thepayasuwan, Hua Tang, Alex Doboli:
An exploration-based binding and scheduling technique for synthesis of digital blocks for mixed-signal applications. 629-632 - Soonhak Kwon, Chang Hoon Kim, Chun Pyo Hong:
A systolic multiplier with LSB first algorithm over GF(2m) which is as efficient as the one with MSB first algorithm. 633-636 - Yonghee Im, Kaushik Roy:
A logic-aware layout methodology to enhance the noise immunity of domino circuits. 637-640 - Wu Jigang, Thambipillai Srikanthan:
Partial rerouting algorithm for reconfigurable VLSI arrays. 641-644 - Mineo Kaneko, Kazuaki Oshio:
Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism. 645-648 - Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano:
A fault tolerant hardware based file system manager for solid state mass memory. 649-652 - Patrice Fleury, Alan F. Murray:
Mixed-signal VLSI implementation of the Products of Experts' contrastive divergence learning scheme. 653-656 - Akira Hirose, Kazuhiko Nakazawa:
Analog continuous-time recurrent decision circuit with high signal-voltage symmetry and delay-time equality. 657-660 - Harish K. Kashyap, Bansilal, P. Arun Koushik:
Hybrid neural network architecture for age identification of ancient Kannada scripts. 661-664 - Hoda S. Abdel-Aty-Zohdy, Jacob N. Allen, Robert L. Ewing:
Plastic NNs for biochemical detection. 665-668 - Mohammed A. Hasan:
Algorithms for computating principal and minor invariant subspaces of large matrices. 669-672 - Hongxia Wang, Chen He, Juebang Yu:
Analysis of global exponential stability for a class of bidirectional associative memory networks. 673-676 - M. Saubhayana, R. W. Newcomb:
Synthesis for symmetric weight matrices of neural networks. 677-680 - Changyin Sun, Changgui Sun, Chun-Bo Feng:
Exponential periodicity of neural networks with delays. 681-684 - Amine Bermak:
A highly scalable 3D chip for binary neural network classification applications. 685-688 - Radu Dogaru, Ioana Dogaru, Manfred Glesner:
Compact image compression using simplicial and ART neural systems with mixed signal implementations. 689-692 - QingNian Zhang, XiangYang He, JianQi Liu:
RBF network based on genetic algorithm optimization for nonlinear time series prediction. 693-696 - Ewan Mardhana, Tohru Ikeguchi:
Neurosearch: a program library for neural network driven search meta-heuristics. 697-700 - Gilson A. Alencar, Luiz Pereira Calôba, Mauro S. Assis:
Artificial neural networks as rain attenuation predictors in earth-space paths. 701-704 - Giovanni Tummarello, Fabio Nardini, Francesco Piazza:
Stepsize control in NLMS acoustic echo cancellation using a neural network. 705-708 - Hongmei Yan, Jun Zheng, Yingtao Jiang, Chenglin Peng, Qinghui Li:
Development of a decision support system for heart disease diagnosis using multilayer perceptron. 709-712 - Stefano Squartini, Amir Hussain, Francesco Piazza:
Preprocessing based solution for the vanishing gradient problem in recurrent neural networks. 713-716 - Jeong-Yon Shim, Lei Xu:
Medical data mining model for oriental medicine via BYY Binary Independent Factor Analysis. 717-720 - Sabri Arik:
Global asymptotic stability of a larger class of delayed neural networks. 721-724 - Hong Ye, Zhiping Lin:
Global optimization of neural network weights using subenergy tunneling function and ripple search. 725-728 - Adrian Burian, Jarmo Takala:
A recurrent neural network for 1-D phase retrieval. 729-732 - Yigang He, Yanghong Tan, Yichuang Sun:
Class-based neural network method for fault location of large-scale analogue circuits. 733-736 - Kenya Jin'no, Hiroshi Taguchi, Takao Yamamoto, Haruo Hirose:
Dynamical hysteresis neural networks for graph coloring problem. 737-740 - Thanapant Raicharoen, Chidchanok Lursinsap, Paron Sanguanbhokai:
Application of critical support vector machine to time series prediction. 741-744 - Antonio Luchetta, Carmine Serio, M. Viggiano:
A neural network to retrieve atmospheric parameters from infrared high resolution sensor spectra. 745-748 - José A. Calderón-Martínez, Pascual Campoy Cervera:
A convolutional neural architecture: an application for defects detection in continuous manufacturing systems. 749-752 - Neyir Ozcan, Sabri Arik, Vedat Tavsanoglu:
New criteria for the existence of stable equilibrium points in nonsymmetric cellular neural networks. 753-756 - Jonne Poikonen, Ari Paasio:
An area-efficient full-wave current rectifier for analog array processing. 757-760 - Gianluca Giustolisi, Alessandro Rizzo:
CMOS implementation of an extended CNN cell to deal with complex dynamics. 761-764 - Fernando Corinto, Marco Gilli, Pier Paolo Civalleri:
On dynamic behavior of full range CNNs. 765-768 - Hyongsuk Kim, Seungwan Hong, Hongrak Son, Tamás Roska, Frank S. Werblin:
High speed road boundary detection on the images for autonomous vehicle with the multi-layer CNN. 769-772 - Radu P. Matei:
Cellular neural networks with second-order cells and their pattern forming properties. 773-776 - P. Barrera, Antonino Calabrò, Luigi Fortuna, Domenico Porto:
A new method for implementing gate operations in a quantum factoring algorithm. 777-780 - Marco Gilli, Paolo Checco, Fernando Corinto:
Periodic orbits and bifurcations in one-dimensional arrays of Chua's circuits. 781-784 - Wasimon Panichpattanakul, Watit Benjapolakul:
Fuzzy power control with weighting function in DS-CDMA cellular mobile communication system. 785-788 - Phayung Meesad, Gary G. Yen:
Fuzzy temporal representation and reasoning. 789-792 - Maide Bucolo, Luigi Fortuna, Manuela La Rosa:
Synchronization in arrays of fuzzy chaotic oscillators. 793-796 - Felix Homburg, Rogelio Palomera-Garcia:
A high speed scalable and reconfigurable fuzzy controller. 797-800 - Janusz A. Starzyk, Tsun-Ho Liu:
Design of a Self-Organizing Learning Array system. 801-804 - Shahed Shahir, Xiang Chen, Majid Ahmadi:
Fuzzy Associative Database for multiple planar object recognition. 805-808 - Suphakant Phimoltares, Chidchanok Lursinsap, Kosin Chamnongthai:
Tight bounded localization of facial features with color and rotational independence. 809-812 - Matteo Perenzoni, Andrea Gerosa, Andrea Neviani:
Analog CMOS implementation of Gallager's iterative decoding algorithm applied to a block turbo code. 813-816 - Adria Bofill-i-Petit, Alan F. Murray:
Learning temporal correlations in biologically-inspired aVLSI. 817-820 - Hiroomi Hikawa:
Pulse mode neuron with leakage integrator and additive random noise. 821-824 - Vladimir Brajovic:
Lossless non-arbitrated address-event coding. 825-828 - Shih-Chii Liu:
A wide-field direction-selective aVLSI spiking neuron. 829-832 - Amine Bermak, Matihias Hojinger:
Focal plane image segmentation using locally interconnected spiking pixel architecture. 833-836 - Dongming Xu, Liping Deng, John G. Harris, José Carlos Príncipe:
Design of a reduced KII set and network in analog VLSI. 837-840
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-06-16 20:51 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
