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Yean-Ru Chen
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2020 – today
- 2024
- [j9]Yean-Ru Chen, Chi-Chieh Chiu, Hang Chen:
Robustness Analysis of Neural Network Designs with Sparsity Investigation. J. Inf. Sci. Eng. 40(3): 595-614 (2024) - [c12]Shang-Wei Lin, Tzu-Fan Wang, Yean-Ru Chen, Zhe Hou
, David Sanán, Yon Shin Teo:
A Parallel and Distributed Quantum SAT Solver Based on Entanglement and Teleportation. TACAS (2) 2024: 363-382 - 2023
- [j8]Yean-Ru Chen
, Tzu-Fan Wang, Si-Han Chen, Yi-Chun Kao:
Empirical study on security verification and assessment of neural network accelerator. Microprocess. Microsystems 99: 104845 (2023) - [j7]Yean-Ru Chen
, Si-Han Chen
, Shangwei Lin
:
SMT Solver With Hardware Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 2055-2068 (2023) - [i2]Shang-Wei Lin, Si-Han Chen, Tzu-Fan Wang, Yean-Ru Chen:
A Quantum SMT Solver for Bit-Vector Theory. CoRR abs/2303.09353 (2023) - [i1]Shang-Wei Lin, Tzu-Fan Wang, Yean-Ru Chen, Zhe Hou, David Sanán, Yon Shin Teo:
A Parallel and Distributed Quantum SAT Solver Based on Entanglement and Quantum Teleportation. CoRR abs/2308.03344 (2023) - 2022
- [j6]Ting-Yu Lin, Ching-Yuan Wang, Ya-Pei Tuan, Meng-Hsun Tsai, Yean-Ru Chen:
A Study on Traffic Asymmetry for Detecting DDoS Attack in P4-based SDN. J. Inf. Sci. Eng. 38(6): 1265-1283 (2022) - [c11]Chien-Hsiang Lin, Yi-Pei Su, Yean-Ru Chen, Yu-Ting Chou, Sao-Jie Chen:
Empirical Study of Proposed Meltdown Attack Implementation on BOOM v3. MWSCAS 2022: 1-4 - [c10]Hang Chen, Yi-Pei Su, Yean-Ru Chen, Chi-Chieh Chiu, Sao-Jie Chen:
Robustness Analysis of Neural Network Designs for ReLU Family and Batch Normalization. TAAI 2022: 1-6
2010 – 2019
- 2014
- [j5]Yean-Ru Chen, Jia-Jen Yeh, Pao-Ann Hsiung, Sao-Jie Chen
:
Accelerating Coverage Estimation Through Partial Model Checking. IEEE Trans. Computers 63(7): 1613-1625 (2014) - [c9]Yean-Ru Chen, Sao-Jie Chen
, Pao-Ann Hsiung, I-Hsin Chou:
Unified Security and Safety Risk Assessment - A Case Study on Nuclear Power Plant. TSA 2014: 22-28 - 2013
- [c8]Yean-Ru Chen, Zi-Rong Wangt, Pao-Ann Hsiung, Sao-Jie Chen
, Meng-Hsun Tsai
:
Backward probing deadlock detection for networks-on-chip. NOCS 2013: 1-2 - 2012
- [c7]Hung-Lin Chao, Yean-Ru Chen, Sheng-Ya Tong, Pao-Ann Hsiung, Sao-Jie Chen:
Congestion-aware scheduling for NoC-based reconfigurable systems. DATE 2012: 1561-1566 - 2011
- [j4]Chao-Sheng Lin, Chun-Hsien Lu, Shang-Wei Lin
, Yean-Ru Chen, Pao-Ann Hsiung:
VERTAF/Multi-Core: A SysML-Based Application Framework for Multi-Core Embedded Software Development. J. Comput. Sci. Technol. 26(3): 448-462 (2011)
2000 – 2009
- 2009
- [j3]Pao-Ann Hsiung, Shang-Wei Lin
, Yean-Ru Chen, Chun-Hsian Huang, Chihhsiong Shih, William C. Chu:
Modeling and verification of real-time embedded systems with urgency. J. Syst. Softw. 82(10): 1627-1641 (2009) - [c6]Yean-Ru Chen, To-Yu Chen, Pao-Ann Hsiung, Sao-Jie Chen, Yu Hen Hu:
Compositional Automata Reduction with Non-critical Path Slicing. FCS 2009: 133-138 - [c5]Pao-Ann Hsiung, Chao-Sheng Lin, Shang-Wei Lin
, Yean-Ru Chen, Chun-Hsien Lu, Sheng-Ya Tong, Wan-Ting Su, Chihhsiong Shih, Chorng-Shiuh Koong, Nien-Lin Hsueh, Chih-Hung Chang
, William C. Chu:
VERTAF/Multi-Core: A SysML-Based Application Framework for Multi-Core Embedded Software Development. ICA3PP 2009: 303-314 - [c4]Pao-Ann Hsiung, Shang-Wei Lin
, Yean-Ru Chen, Nien-Lin Hsueh, Chih-Hung Chang
, Chihhsiong Shih, Chorng-Shiuh Koong, Chao-Sheng Lin, Chun-Hsien Lu, Sheng-Ya Tong, Wan-Ting Su, William C. Chu:
Model-driven development of multi-core embedded software. IWMSE@ICSE 2009: 9-16 - 2007
- [j2]Yean-Ru Chen, Pao-Ann Hsiung:
Automatic Failure Analysis Using Safecharts. Int. J. Softw. Eng. Knowl. Eng. 17(1): 57-78 (2007) - [j1]Pao-Ann Hsiung, Yean-Ru Chen, Yen-Hung Lin:
Model Checking Safety-Critical Systems Using Safecharts. IEEE Trans. Computers 56(5): 692-705 (2007) - [c3]Yean-Ru Chen, Pao-Ann Hsiung, Sao-Jie Chen:
Modeling and Automatic Failure Analysis of Safety-Critical Systems Using Extended Safecharts. SAFECOMP 2007: 451-464 - 2006
- [c2]Pao-Ann Hsiung, Shang-Wei Lin, Yean-Ru Chen, Chun-Hsian Huang, Jia-Jen Yeh, Hong-Yu Sun, Chao-Sheng Lin, Hsiao-Win Liao:
Model Checking Timed Systems with Urgencies. ATVA 2006: 67-81 - 2005
- [c1]Shang-Wei Lin
, Pao-Ann Hsiung, Chun-Hsian Huang, Yean-Ru Chen:
Model Checking Prioritized Timed Automata. ATVA 2005: 370-384
Coauthor Index
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last updated on 2024-08-05 20:18 CEST by the dblp team
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