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ORCIDDATE 2012: Dresden, Germany
- Wolfgang Rosenstiel, Lothar Thiele:
2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012. IEEE 2012, ISBN 978-1-4577-2145-8
Keynote Addresses
- Klaus Meder:
The mobile society - chances and challenges for micro- and power electronics. 1 - Mojy Chian:
New foundry models - accelerations in transformations of the semiconductor industry. 2
Validation of Modern Microprocessors
- Xiaoke Qin, Prabhat Mishra:
Automated generation of directed tests for transition coverage in cache coherence protocols. 3-8 - Eberle A. Rambo, Olav P. Henschel, Luiz C. V. dos Santos
:
On ESL verification of memory consistency for system-on-chip multiprocessing. 9-14 - Yoav Katz, Michal Rimon, Avi Ziv:
Generating instruction streams using abstract CSP. 15-20 - Timo Stripf, Ralf König, Jürgen Becker:
A cycle-approximate, mixed-ISA simulator for the KAHRISMA architecture. 21-26 - Jianliang Gao, Jianxin Wang, Yinhe Han, Lei Zhang, Xiaowei Li:
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems. 27-32
Memory System Optimization
- Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi:
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. 33-38 - Srdjan Stipic, Sasa Tomic, Ferad Zyulkyarov, Adrián Cristal, Osman S. Ünsal, Mateo Valero:
TagTM - accelerating STMs with hardware tags for fast meta-data access. 39-44 - Giuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli:
Enabling dynamic assertion-based verification of embedded software through model-driven design. 212-217 - Yu-Ting Chen, Jason Cong, Hui Huang, Bin Liu, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman:
Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. 45-50 - Manil Dev Gomony, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens:
DRAM selection and configuration for real-time mobile systems. 51-56
Architectures and Efficient Designs for Automotive and Energy-Management Systems
- Jonas Rox, Rolf Ernst, Paolo Giusto:
Using timing analysis for the design of future switched based Ethernet automotive networks. 57-62 - Chun Zhang, Wei Wu, Hantao Huang, Hao Yu:
Fair energy resource allocation by minority game algorithm for smart buildings. 63-68 - Christoph Schmutzler, Martin Simons, Jürgen Becker:
On demand dependent deactivation of automotive ECUs. 69-74 - Michele Magno, Stevan Jovica Marinkovic, Davide Brunelli, Emanuel M. Popovici, Brendan O'Flynn, Luca Benini:
Smart power unit with ultra low power radio trigger capabilities for wireless sensor networks. 75-80
Physical Design for Low-Power
- Sandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino:
IR-drop analysis of graphene-based power distribution networks. 81-86 - Keheng Huang, Yu Hu, Xiaowei Li, Bo Liu, Hongjin Liu, Jian Gong:
Off-path leakage power aware routing for SRAM-based FPGAs. 87-92 - Adam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara:
Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization. 93-98 - Mohammad Rahman, Carl Sechen:
Post-synthesis leakage power minimization. 99-104
Optimized Utilization of Embedded Platforms
- Andrea Marongiu, Paolo Burgio, Luca Benini:
Fast and lightweight support for nested parallelism on cluster-based embedded many-cores. 105-110 - Iraklis Anagnostopoulos, Alexandros Bartzas, Georgios Kathareios, Dimitrios Soudris:
A divide and conquer based distributed run-time mapping methodology for many-core platforms. 111-116 - Wen-Huei Lin, Li-Pin Chang:
Dual Greedy: Adaptive garbage collection for page-mapping solid-state disks. 117-122
Special Session - Hot Topic - EDA Solutions to New-Defect Detection in Advanced Process Technologies
- Erik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl:
EDA solutions to new-defect detection in advanced process technologies. 123-128
Beyond CMOS - Benchmarking for Future Technologies
- Clivia M. Sotomayor Torres, Jouni Ahopelto, Mart W. M. Graef, R. M. Popp, Wolfgang Rosenstiel:
Beyond CMOS - benchmarking for future technologies. 129-134
Effective Functional Simulation and Validation
- Kun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Accurately timed transaction level models for virtual prototyping at high abstraction level. 135-140 - Weiwei Chen, Xu Han, Rainer Dömer:
Out-of-order parallel simulation for ESL design. 141-146 - Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen:
A probabilistic analysis method for functional qualification under Mutation Analysis. 147-152 - Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco:
Approximating checkers for simulation acceleration. 153-158
Industrial Design Methodologies
- Dierk Steinbach:
Guidelines for model based systems engineering. 159-160 - Niccolò Battezzati, Stefano Colazzo, M. Maffione, L. Senepa:
SURF algorithm in FPGA: A novel architecture for high demanding industrial applications. 161-162 - Omar Hammami, Xinyu Li, Jean-Marc Brault:
NOCEVE: Network on chip emulation and verification environment. 163-164 - Alessandro Sassone, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Richard Goldman, Vazgen Melikyan, Eduard Babayan, Salvatore Rinaudo:
Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networks. 165-166 - Tsunwai Gary Yip, Chuan Yung Hung, Venu Iyengar:
Challenges in verifying an integrated 3D design. 167-168
Large-Scale Energy and Thermal Management
- Yanzhi Wang, Qing Xie, Massoud Pedram, Younghyun Kim, Naehyuck Chang, Massimo Poncino:
Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systems. 169-174 - Baris Aksanli, Tajana Simunic Rosing, Inder Monga:
Benefits of green energy and proportionality in high speed wide area networks connecting data centers. 175-180 - Andrea Bartolini, MohammadSadegh Sadri, John-Nicholas Furst, Ayse Kivilcim Coskun, Luca Benini:
Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computer. 181-186 - Guanglei Liu, Ming Fan, Gang Quan:
Neighbor-aware dynamic thermal management for multi-core platform. 187-192
Model-Based Design and Verification for Embedded Systems
- Yang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal:
Playing games with scenario- and resource-aware SDF graphs through policy iteration. 194-199 - A. C. Rajeev, Swarup Mohalik, S. Ramesh:
Verifying timing synchronization constraints in distributed embedded architectures. 200-205 - Marco Di Natale, Haibo Zeng:
Task implementation of synchronous finite state machines. 206-211
Improving Reliability and Yield in Advanced Technologies
- Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori:
NBTI mitigation by optimized NOP assignment and insertion. 218-223 - Julian J. H. Pontes, Ney Calazans, Pascal Vivet:
An accurate Single Event Effect digital design flow for reliable system level design. 224-229 - Mohammed Abdul Shahid:
Cross entropy minimization for efficient estimation of SRAM failure rate. 230-235
Hot Topic - Design Automation Tools for Engineering Biological Systems
- Boyan Yordanov, Evan Appleton, Rishi Ganguly, Ebru Aydin Gol, Swati Banerjee Carr, Swapnil Bhatia, Traci Haddock, Calin Belta, Douglas Densmore:
Experimentally driven verification of synthetic biological circuits. 236-241 - Soha Hassoun:
Genetic/bio design automation for (re-)engineering biological systems. 242-247
Interactive Presentations
- David Thach, Yutaka Tamiya, Shinya Kuwamura, Atsushi Ike:
Fast cycle estimation methodology for instruction-level emulator. 248-251 - Etem Deniz, Alper Sen, Jim Holt:
Verification coverage of embedded multicore applications. 252-255 - Padmaraj Singh, Vijaykrishnan Narayanan, David L. Landis:
Hazard driven test generation for SMT processors. 256-259 - Chundong Wang, Weng-Fai Wong:
Extending the lifetime of NAND flash memory by salvaging bad blocks. 260-263 - Suknam Kwon, Dongki Kim, Youngsik Kim, Sungjoo Yoo, Sunggu Lee:
A case study on the application of real phase-change RAM to main memory subsystem. 264-267 - Henning Sahlbach, Sean Whitty, Rolf Ernst:
A high-performance dense block matching solution for automotive 6D-vision. 268-271 - Mahsan Rofouei, Mohammad Ali Ghodrat, Miodrag Potkonjak, Alfonso Martinez-Nova:
Optimization intensive energy harvesting. 272-275 - Paul Milbredt, Michael Glaß, Martin Lukasiewycz, Andreas Steininger, Jürgen Teich:
Designing FlexRay-based automotive architectures: A holistic OEM approach. 276-279 - Stephan Werner, Oliver Oey, Diana Göhringer, Michael Hübner, Jürgen Becker:
Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systems. 280-283 - Luis Angel D. Bathen, Nikil D. Dutt, Alex Nicolau, Puneet Gupta:
VaMV: Variability-aware Memory Virtualization. 284-287 - Jovana Jovic, Sergey Yakoushkin, Luis Gabriel Murillo, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid:
Hybrid simulation for extensible processor cores. 288-291 - Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le:
Leveraging reconfigurability to raise productivity in FPGA functional debug. 292-295 - Markus Becker, Gilles B. Defo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, Sara Vinco:
MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolution. 296-299 - Yue Wang, Soumyaroop Roy, Nagarajan Ranganathan:
Run-time power-gating in caches of GPUs for leakage energy savings. 300-303 - Fei Sun:
Automatic generation of functional models for embedded processor extensions. 304-307 - Prakash Mohan Peranandam, Sachin Raviram, Manoranjan Satpathy, Anand Yeolekar, Ambar A. Gadkari, S. Ramesh:
An integrated test generation tool for enhanced coverage of Simulink/Stateflow models. 308-311 - Michaël Lafaye, Laurent Pautet, Etienne Borde, Marc Gatti, David Faura:
Model driven resource usage simulation for critical embedded systems. 312-315 - Min Li, Michael S. Hsiao:
RAG: An efficient reliability analysis of logic circuits on graphics processing units. 316-319
Routing Solutions for Upcoming NoC Challenges
- Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
CATRA- congestion aware trapezoid-based routing algorithm for on-chip networks. 320-325 - Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy:
An MILP-based aging-aware routing algorithm for NoCs. 326-331 - Sara Akbari, Ali Shafiee, Mahmood Fathy, Reza Berangi:
AFRA: A low cost high performance reliable routing for 3D mesh NoCs. 332-337
Industrial Embedded System Design
- Edoardo Patti, Andrea Acquaviva, Francesco Abate, Anna Osello, A. Cocuccio, Marco Jahn, Marc Jentsch, Enrico Macii:
Middleware services for network interoperability in smart energy efficient buildings. 338-339 - Mauro Turturici, Sergio Saponara, Luca Fanucci, Emilio Franchi:
Low-power embedded system for real-time correction of fish-eye automotive cameras. 340-341 - Monica Donno, Aleck Ferrari, Annalisa Scarpelli, Pietro Perlo, Alberto Bocca:
Mechatronic system for energy efficiency in bus transport. 342-343 - Mohammad Abdullah Al Faruque, Arquimedes Canedo:
Intelligent and collaborative embedded computing in automation engineering. 344-345
System-Level Power and Reliability Estimation and Optimization
- Yang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich:
Variation-aware leakage power model extraction for system-level hierarchical power analysis. 346-351 - Hai Wang, Sheldon X.-D. Tan, Xuexin Liu, Ashish Gupta:
Runtime power estimator calibration for high-performance microprocessors. 352-357 - Norbert Druml, Christian Steger, Reinhold Weiss, Andreas Genser, Josef Haid:
Estimation based power and supply voltage management for future RF-powered multi-core smart cards. 358-363 - Haroon Mahmood, Massimo Poncino, Mirko Loghi, Enrico Macii:
Application-specific memory partitioning for joint energy and lifetime optimization. 364-369
Embedded Tutorial - State-of-the-Art Tools and Techniques for Quantitative Modeling and Analysis of Embedded Systems
- Marius Bozga, Alexandre David, Arnd Hartmanns, Holger Hermanns, Kim G. Larsen, Axel Legay, Jan Tretmans:
State-of-the-art tools and techniques for quantitative modeling and analysis of embedded systems. 370-375
Compilers and Source-Level Simulation
- Stefan Stattelmann, Gernot Gebhard, Christoph Cullmann, Oliver Bringmann, Wolfgang Rosenstiel:
Hybrid source-level simulation of data caches using abstract cache models. 376-381 - Zhonglei Wang, Jörg Henkel:
Accurate source-level simulation of embedded software with respect to compiler optimizations. 382-387 - Dongrui She, Yifan He, Bart Mesman, Henk Corporaal:
Scheduling for register file energy minimization in explicit datapath architectures. 388-393 - Daniel Cordes, Peter Marwedel:
Multi-objective aware extraction of task-level parallelism using genetic algorithms. 394-399
Advances in Test Generation
- Kai-Hui Chang, Hong-Zu Chou, Igor L. Markov:
RTL analysis and modifications for improving at-speed test. 400-405 - Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil:
Test generation for clock-domain crossing faults in integrated circuits. 406-411 - Davide Sabena, Matteo Sonza Reorda, Luca Sterpone:
A new SBST algorithm for testing the register file of VLIW processors. 412-417 - Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian:
On the optimality of K longest path generation algorithm under memory constraints. 418-423
Special Day E-Mobility - Embedded Systems and SW Challenges
- Samarjit Chakraborty, Martin Lukasiewycz, Christian Buckl, Suhaib A. Fahmy, Naehyuck Chang, Sangyoung Park, Younghyun Kim, Patrick Leteinturier, Hans Adlkofer:
Embedded systems and software challenges in electric vehicles. 424-429
Panel - Accelerators and Emulatiors for HS Verification
- Bashir M. Al-Hashimi, Ronny Morad:
Accelerators and emulators: Can they become the platform of choice for hardware verification? 430
Medical and Healthcare Applications
- Mohammed Shoaib, Gene Marsh, Harinath Garudadri, Somdeb Majumdar:
A closed-loop system for artifact mitigation in ambulatory electrocardiogram monitoring. 431-436 - Mohammed Shoaib, Niraj K. Jha, Naveen Verma:
Enabling advanced inference on sensor nodes through direct use of compressively-sensed signals. 437-442 - Geng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng:
A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare system. 443-448
Microarchitecture
- Mingxing Tan, Xianhua Liu, Zichao Xie, Dong Tong, Xu Cheng:
Energy-efficient branch prediction with Compiler-guided History Stack. 449-454 - Maryam Sadooghi-Alvandi, Kaveh Aasaraai, Andreas Moshovos:
Toward virtualizing branch direction prediction. 455-460 - Xianglei Dang, Xiaoyin Wang, Dong Tong, Junlin Lu, Jiangfang Yi, Keyi Wang:
S/DC: A storage and energy efficient data prefetcher. 461-466 - Mehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram:
An architecture-level approach for mitigating the impact of process variations on extensible processors. 467-472
Shared Memory Management in Multicore
- Konstantinos Aisopos, Jaideep Moses, Ramesh Illikkal, Ravishankar R. Iyer, Donald Newell:
PCASA: Probabilistic control-adjusted Selective Allocation for shared caches. 473-478 - Abhishek Das, Matthew Schuchhardt, Nikos Hardavellas, Gokhan Memik, Alok N. Choudhary:
Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores. 479-484 - Fazal Hameed, Lars Bauer, Jörg Henkel:
Dynamic cache management in multi-core architectures through run-time adaptation. 485-490 - José L. Abellán, Juan Fernández Peinador, Manuel E. Acacio, Davide Bertozzi, Daniele Bortolotti, Andrea Marongiu, Luca Benini:
Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs. 491-496
Scheduling and Allocation
- José Marinho, Vincent Nélis, Stefan M. Petters, Isabelle Puaut:
Preemption delay analysis for floating non-preemptive region scheduling. 497-502 - Ming Fan, Gang Quan:
Harmonic semi-partitioned scheduling for fixed-priority real-time tasks on multi-core platform. 503-508 - Jia Huang, Jan Olaf Blech, Andreas Raabe, Christian Buckl, Alois C. Knoll:
Static scheduling of a Time-Triggered Network-on-Chip based on SMT solving. 509-514 - Sophie Quinton, Matthias Hanke, Rolf Ernst:
Formal analysis of sporadic overload in real-time systems. 515-520
Testing of Non-Volatile Memories
- Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai:
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. 521-526 - Jin Zha, Xiaole Cui, Chung Len Lee:
Modeling and testing of interference faults in the nano NAND Flash memory. 527-531 - Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay:
Impact of resistive-open defects on the heat current of TAS-MRAM architectures. 532-537
Interactive Presentations
- Fahimeh Jafari, Axel Jantsch, Zhonghai Lu:
Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate scheduling. 538-541 - Giorgos Dimitrakopoulos, Emmanouil Kalligeros:
Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switches. 542-545 - Shuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan:
Low power aging-aware register file design by duty cycle balancing. 546-549 - Nainala Vyagrheswarudu, Subrangshu Das, Abhishek Ranjan:
PowerAdviser: An RTL power platform for interactive sequential optimizations. 550-553 - Arquimedes Canedo, Mohammad Abdullah Al Faruque:
Towards parallel execution of IEC 61131 industrial cyber-physical systems applications. 554-557 - Kameshwar Chandrasekar, Supratik K. Misra, Sanjay Sengupta, Michael S. Hsiao:
A scan pattern debugger for partial scan industrial designs. 558-561 - Nicola Bombieri, Franco Fummi, Valerio Guarnieri:
FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs. 562-565 - Sebastiano Pomata, Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Menno Lindwer:
Exploiting binary translation for fast ASIP design space exploration on FPGAs. 566-569 - Cedric Walravens, Wim Dehaene:
Design of a low-energy data processing architecture for WSN nodes. 570-573 - Hamed Tabkhi, Gunar Schirner:
Application-specific power-efficient approach for reducing register file vulnerability. 574-577 - Raphael Guerra, Gerhard Fohler:
On-line scheduling of target sensitive periodic tasks with the gravitational task model. 578-581 - Liang Chen, Thomas Marconi, Tulika Mitra:
Online scheduling for multi-core shared reconfigurable fabric. 582-585 - Abbas Mohammadi, Mojtaba Ebrahimi, Alireza Ejlali, Seyed Ghassem Miremadi:
SCFIT: A FPGA-based fault injection technique for SEU fault model. 586-589
Keynote Address
- Thierry Van der Pyl:
Research and innovation on Advanced Computing - an EU perspective. 591
Embedded Tutorial - Memristor Technology
- Ronald Tetzlaff, Andreas Bruening:
Memristor technology in future electronic system design. 592
Thermal Aware Low Power Design
- Shervin Sharifi, Raid Zuhair Ayoub, Tajana Simunic Rosing:
TempoMP: Integrated prediction and management of temperature in heterogeneous MPSoCs. 593-598 - Mohamed M. Sabry, Arvind Sridhar, David Atienza:
Thermal balancing of liquid-cooled 3D-MPSoCs using channel modulation. 599-604 - Da-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang:
Statistical thermal modeling and optimization considering leakage power variations. 605-610 - Jie Meng, Ayse K. Coskun:
Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiency. 611-616
Basic Techniques for Improving the Formal Verification Flow
- Finn Haedicke, Daniel Große, Rolf Drechsler:
A guiding coverage metric for formal verification. 617-622 - Paolo Marin, Christian Miller, Matthew Lewis, Bernd Becker:
Verification of partial designs using incremental QBF solving. 623-628 - Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris:
Non-solution implications using reverse domination in a modern SAT-based debugging environment. 629-634
System-on-Chip Composition and Synthesis
- Daniel Thiele, Rolf Ernst:
Optimizing performance analysis for synchronous dataflow graphs with shared resources. 635-640 - Hung-Yi Liu, Michele Petracca, Luca P. Carloni:
Compositional system-level design exploration with planning of high-level synthesis. 641-646 - Roopak Sinha, Partha S. Roop, Zoran Salcic, Samik Basu:
Correct-by-construction multi-component SoC design. 647-652
Timing Analysis
- Bart D. Theelen, Joost-Pieter Katoen, Hao Wu:
Model checking of Scenario-Aware Dataflow with CADP. 653-658 - Aayush Prakash, Hiren D. Patel:
An instruction scratchpad memory allocation for the precision timed architecture. 659-664 - Hardik Shah, Andreas Raabe, Alois C. Knoll:
Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCs. 665-670 - Mike Gerdes, Florian Kluge, Theo Ungerer, Christine Rochange, Pascal Sainrat:
Time analysable synchronisation techniques for parallelised hard real-time applications. 671-676
Hot Topic - Design for Test and Reliability in Ultimate CMOS
- Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky:
Design for test and reliability in ultimate CMOS. 677-682
Hot Topic - Energy of Optimization (Special Day E-Mobility)
- Kosmas Knoedler, Jochen Steinmann, Sylvain Laversanne, Stephen Jones, Arno Huss, Emre Kural, David Sanchez, Oliver Bringmann, Jochen Zimmermann:
Optimal energy management and recovery for FEV. 683-684
Hot Topic - Virtual Platforms: Breaking New Grounds
- Rainer Leupers, Grant Martin, Roman Plyaskin, Andreas Herkersdorf, Frank Schirrmeister, Tim Kogel, Martin Vaupel:
Virtual platforms: Breaking new grounds. 685-690
Multimedia and Consumer Applications
- Mi Sun Park, Srinidhi Kestur, Jagdish Sabarad, Vijaykrishnan Narayanan, Mary Jane Irwin:
An FPGA-based accelerator for cortical object classification. 691-696 - Muhammad Shafique, Bruno Zatt, Semeen Rehman, Florian Kriebel, Jörg Henkel:
Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding. 697-702 - Christos Ttofis, Theocharis Theocharides:
Towards accurate hardware stereo correspondence: A real-time FPGA implementation of a segmentation-based adaptive support weight algorithm. 703-708 - Georgios Chatziparaskevas, Andreas Brokalakis, Ioannis Papaefstathiou:
An FPGA-based parallel processor for Black-Scholes option pricing using finite differences schemes. 709-714
Nanoelectronic Devices
- Lukás Sekanina, Zdenek Vasícek:
A SAT-based fitness function for evolutionary optimization of polymorphic circuits. 715-720 - Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
Mach-Zehnder interferometer based design of all optical reversible binary adder. 721-726 - Shruti Patil, Min-Woo Jang, Chia-Ling Chen, Dongjin Lee, Zhijang Ye, Walter E. Partlo, David J. Lilja, Stephen A. Campbell, Tianhong Cui:
Weighted area technique for electromechanically enabled logic computation with cantilever-based NEMS switches. 727-732
High Level and Statistical Design of Mixed-Signal Systems
- Leran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Mansour Aloufi, Joseph Wenninger:
Response-surface-based design space exploration and optimisation of wireless sensor nodes with tunable energy harvesters. 733-738 - Antoine Lévêque, François Pêcheux, Marie-Minerve Louërat, Hassan Aboushady, Fabio Cenni, Serge Scotti, Abdelbasset Massouri, Laurent Clavier:
Holistic modeling of embedded systems with multi-discipline feedback: Application to a Precollision Mitigation Braking System. 739-744 - Elie Maricau, Dimitri de Jonghe, Georges G. E. Gielen:
Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection. 745-750 - Bo Liu, Jarir Messaoudi, Georges G. E. Gielen:
A fast analog circuit yield estimation method for medium and high dimensional problems. 751-756 - Markus Meissner, Oliver Mitea, Linda Luy, Lars Hedrich:
Fast isomorphism testing for a graph-based analog circuit synthesis framework. 757-762
Advances in Dataflow Modeling and Analysis
- Abdoulaye Gamatié:
Design of streaming applications on MPSoCs using abstract clocks. 763-768 - Pascal Fradet, Alain Girault, Peter Poplavko:
SPDF: A schedulable parametric data-flow MoC. 769-774 - Morteza Damavandpeyma, Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal:
Modeling static-order schedules in synchronous dataflow graphs. 775-780 - Roberta Piscitelli, Andy D. Pimentel:
Design space pruning through hybrid analysis in system-level design space exploration. 781-786
Test and Repair of New Technologies
- Michael Richter, Krishnendu Chakrabarty:
Test pin count reduction for NoC-based Test delivery in multicore SOCs. 787-792 - Li Jiang, Qiang Xu, Bill Eklow:
On effective TSV repair for 3D-stacked ICs. 793-798 - Nor Zaidi Haron, Said Hamdioui:
DfT schemes for resistive open defects in RRAMs. 799-804
Hot Topic - New Directions in Timing Modeling and Analysis of Automotive Software
- Marie-Agnès Peraldi-Frati, Hans Blom, Daniel Karlsson, Stefan Kuntz:
Timing Modeling with AUTOSAR - Current state and future directions. 805-809 - Sophie Quinton, Rolf Ernst, Dominique Bertrand, Patrick Meumeu Yomsi:
Challenges and new trends in probabilistic timing analysis. 810-815
Interactive Presentations
- Huan Chen, Mikolás Janota, João Marques-Silva:
QBf-based boolean function bi-decomposition. 816-819 - Christian Ellen, Christoph Etzien, Markus Oertel:
Automatic transition between structural system views in a safety relevant embedded systems development process. 820-823 - Lukás Sekanina, Vojtech Salajka:
Towards new applications of multi-function logic: Image multi-filtering. 824-827 - Sven Goossens, Tim Kouters, Benny Akesson, Kees Goossens:
Memory-map selection for firm real-time SDRAM controllers. 828-831 - Yun Liang, Zheng Cui, Shengkui Zhao, Kyle Rupnow, Yihao Zhang, Douglas L. Jones, Deming Chen:
Real-time implementation and performance optimization of 3D sound localization on GPUs. 832-835 - Adi Xhakoni, David San Segundo Bello, Georges G. E. Gielen:
Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensors. 836-839 - Mohammad Javad Dousti, Massoud Pedram:
Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabric. 840-843 - Cheng Zhang, Vasilis F. Pavlidis, Giovanni De Micheli:
Voltage propagation method for 3-D power grid analysis. 844-847 - Sergey A. Nazin, Dominique Morche, Alexandre Reinhardt:
Yield optimization for radio frequency receiver at system level. 848-851 - Xuexin Liu, Sheldon X.-D. Tan, Hai Wang:
Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach. 852-857 - Robert Rudolf, Pouya Taatizadeh, Reuben Wilcock, Peter R. Wilson:
Automated critical device identification for configurable analogue transistors. 858-861 - Jochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel:
Analysis of multi-domain scenarios for optimized dynamic power management strategies. 862-865 - Amitabh Das, Ünal Koçabas, Ahmad-Reza Sadeghi, Ingrid Verbauwhede:
PUF-based secure test wrapper design for cryptographic SoC testing. 866-869
Hot Topic - Robustness Challenges in Automotive (Special Day E-Mobility)
- Ulrich Abelein, Helmut Lochner, Daniel Hahn, Stefan Straube:
Complexity, quality and robustness - the challenges of tomorrow's automotive electronics. 870-871 - Thomas Nirmaier, Volker Meyer zu Bexten, Markus Tristl, Manuel Harrant, Matthias Kunze, Monica Rafaila, Julia Lau, Georg Pelz:
Measuring and improving the robustness of automotive smart power microelectronics. 872-873
Panel - EDA for Trailing Edge Technologies
- Marco Casale-Rossi, Pierluigi Rolandi, Andreas Bruening, Antun Domic, Rainer Kress, Joseph Sawicki, Christian Sebeke:
Panel: What is EDA doing for trailing edge technologies? 874
Innovative Reliable Systems and Applications
- Tuo Li, Roshan G. Ragel, Sri Parameswaran:
Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors. 875-880 - Cristian Zambelli, Marco Indaco, Michele Fabiano, Stefano Di Carlo, Paolo Prinetto, Piero Olivo, Davide Bertozzi:
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories. 881-886 - Mohammad Reza Kakoee, Igor Loi, Luca Benini:
A resilient architecture for low latency communication in shared-L1 processor clusters. 887-892 - Isil Öz, Haluk Rahmi Topcuoglu, Mahmut T. Kandemir, Oguz Tosun:
Performance-reliability tradeoff analysis for multithreaded applications. 893-898
Advances in Formal SoC Verification
- Jinpeng Lv, Priyank Kalla, Florian Enescu:
Efficient Gröbner basis reductions for formal verification of galois field multipliers. 899-904 - Sayak Ray, Robert K. Brayton:
Scalable progress verification in credit-based flow-control systems. 905-910 - Srobona Mitra, Ansuman Banerjee, Pallab Dasgupta:
Formal methods for ranking counterexamples through assumption mining. 911-916
Variability and Delay
- Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs:
Transistor-level gate model based statistical timing analysis considering correlations. 917-922 - Christoph Knoth, Hela Jedda, Ulf Schlichtmann:
Current source modeling for power and timing analysis at different supply voltages. 923-928 - Rong Ye, Feng Yuan, Hai Zhou, Qiang Xu:
Clock skew scheduling for timing speculation. 929-934
System-Level Optimization of Embedded Real-Time Systems
- Junhe Gan, Paul Pop, Flavius Gruian, Jan Madsen:
Robust and flexible mapping for real-time distributed applications during the early design phases. 935-940 - Mohamed Bamakhrama, Jiali Teddy Zhai, Hristo Nikolov, Todor P. Stefanov:
A methodology for automated design of hard-real-time embedded streaming systems. 941-946 - Ke Jiang, Petru Eles, Zebo Peng:
Co-design techniques for distributed real-time embedded systems with communication security constraints. 947-952
On-Line Test for Secure Systems
- Jeyavijayan Rajendran, Youngok K. Pino, Ozgur Sinanoglu, Ramesh Karri:
Logic encryption: A fault analysis perspective. 953-958 - Filip Veljkovic, Vladimir Rozic, Ingrid Verbauwhede:
Low-cost implementations of on-the-fly tests for random number generators. 959-964 - Yier Jin, Dzmitry Maliuk, Yiorgos Makris:
Post-deployment trust evaluation in wireless cryptographic ICs. 965-970
Embedded Tutorial - Batteries and Battery Management Systems
- M. Brandl, Harald Gall, Martin M. Wenger, Vincent R. H. Lorentz, Martin Giegerich, Federico Baronti, Gabriele Fantechi, Luca Fanucci, Roberto Roncella, Roberto Saletti, Sergio Saponara, Alexander Thaler, Martin Cifrain, W. Prochazka:
Batteries and battery management systems for electric vehicles. 971-976
Special Session - From Ultra-Low-Power Multi-Core Design to Exascale Computing
- Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger:
Power management of multi-core chips: Challenges and pitfalls. 977-982 - Luca Benini, Eric Flamand, Didier Fuin, Diego Melpignano:
P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator. 983-987 - Ahmed Yasir Dogan, Jeremy Constantin, Martino Ruggiero, Andreas Burg, David Atienza:
Multi-core architecture design for ultra-low-power wearable health monitoring systems. 988-993 - Can Hankendi, Ayse K. Coskun:
Reducing the energy cost of computing through efficient co-scheduling of parallel workloads. 994-999
Architecture and Building Blocks for Secure Systems
- Mark R. Beaumont, Bradley D. Hopkins, Tristan Newby:
SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardware. 1000-1005 - Xu Guo, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, Patrick Schaumont:
ASIC implementations of five SHA-3 finalists. 1006-1011 - Michael Zohner, Michael Kasper, Marc Stöttinger, Sorin A. Huss:
Side channel analysis of the SHA-3 finalists. 1012-1017
Advances in High-Level Synthesis
- Jason Cong, Muhuan Huang, Bin Liu, Peng Zhang, Yi Zou:
Combining module selection and replication for throughput-driven streaming programs. 1018-1023 - Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe:
Exploiting area/delay tradeoffs in high-level synthesis. 1024-1029 - Marcela Zuluaga, Edwin V. Bonilla, Nigel P. Topham:
Predicting best design trade-offs: A case study in processor customization. 1030-1035
Supply Voltage and Circuitry Based Power Reductions
- Robert Wille, Rolf Drechsler, Christof Osewold, Alberto García Ortiz:
Automatic design of low-power encoders using reversible circuit synthesis. 1036-1041 - Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene:
Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM. 1042-1047 - Hamid Reza Pourshaghaghi, Hamed Fatemi, José Pineda de Gyvez:
Sliding-Mode Control to Compensate PVT Variations in dual core systems. 1048-1053 - Kwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong:
MAPG: Memory access power gating. 1054-1059 - Qing Xie, Xue Lin, Yanzhi Wang, Massoud Pedram, Donghwa Shin, Naehyuck Chang:
State of health aware charge management in hybrid electrical energy storage systems. 1060-1065
Creation and Processing of System-level Models
- Vladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann:
Automated construction of a cycle-approximate transaction level model of a memory controller. 1066-1071 - Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia, Francesco Stefanni:
Refinement of UML/MARTE models for the design of networked embedded systems. 1072-1077 - Robert Wille, Mathias Soeken, Rolf Drechsler:
Debugging of inconsistent UML/OCL models. 1078-1083
Test and Monitoring of RF and Mixed-Signal ICs
- Afsaneh Nassery, Sule Ozev:
An analytical technique for characterization of transceiver IQ imbalances in the loop-back mode. 1084-1089 - Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet:
Testing RF circuits with true non-intrusive built-in sensors. 1090-1095 - Jinbo Wan, Hans G. Kerkhoff:
Monitoring active filters under automotive aging scenarios with embedded instrument. 1096-1101
Interactive Presentations
- Abbas Rahimi, Luca Benini, Rajesh K. Gupta:
Analysis of instruction-level vulnerability to dynamic voltage and temperature variations. 1102-1105 - Andrea Pellegrini, Robert Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita V. Adve, Todd M. Austin, Valeria Bertacco:
CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions. 1106-1109 - Mohamed M. Sabry, David Atienza, Francky Catthoor:
A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems. 1110-1113 - Philip Axer, Maurice Sebastian, Rolf Ernst:
Probabilistic response time bound for CAN messages with arbitrary deadlines. 1114-1117 - Xin Fan, Milos Krstic, Eckhard Grass, Birgit Sanders, Christoph Heer:
Exploring pausible clocking based GALS design for 40-nm system integration. 1118-1121 - Shubhyant Chaturvedi:
Static analysis of asynchronous clock domain crossings. 1122-1125 - Bharath Suri, Unmesh D. Bordoloi, Petru Eles:
A scalable GPU-based approach to accelerate the multiple-choice knapsack problem. 1126-1129 - Stéphane Mancini, Frédéric Rousseau:
Enhancing non-linear kernels by an optimized memory hierarchy in a High Level Synthesis flow. 1130-1133 - Abhishek A. Sinkar, Hao Wang, Nam Sung Kim:
Workload-aware voltage regulator optimization for power efficient multi-core processors. 1134-1137 - Christian Weis, Igor Loi, Luca Benini, Norbert Wehn:
An energy efficient DRAM subsystem for 3D integrated SoCs. 1138-1141 - Mathias Soeken, Robert Wille, Rolf Drechsler:
Eliminating invariants in UML/OCL models. 1142-1145 - Hyunjin Kim, Jacob A. Abraham:
On-chip source synchronous interface timing test scheme with calibration. 1146-1149
Special Day More-Than-Moore: Technologies
- Helmut Graeb:
ITRS 2011 Analog EDA Challenges and Approaches. 1150-1155 - Dominique Morche, Michaël Pelissier, Gilles Masson, Pierre Vincent:
UWB: Innovative architectures enable disruptive low power wireless applications. 1156-1160
Pathways to Servers of the Future
- Gerhard P. Fettweis, Wolfgang E. Nagel, Wolfgang Lehner:
Pathways to servers of the future. 1161-1166
Side-Channel Analysis and Protection of Secure Embedded Systems
- Guilherme Perin, Lionel Torres, Pascal Benoit, Philippe Maurine:
Amplitude demodulation-based EM analysis of different RSA implementations. 1167-1172 - Maxime Nassar, Youssef Souissi, Sylvain Guilley, Jean-Luc Danger:
RSM: A small and fast countermeasure for AES, secure against 1st and 2nd-order zero-offset SCAs. 1173-1178 - Annelie Heuser, Werner Schindler, Marc Stöttinger:
Revealing side-channel issues of complex circuits by enhanced leakage models. 1179-1184
Topics in High-Level Synthesis
- Yibo Chen, Guangyu Sun, Qiaosha Zou, Yuan Xie:
3DHLS: Incorporating high-level synthesis in physical planning of three-dimensional (3D) ICs. 1185-1190 - John Hansen, Montek Singh:
Multi-token resource sharing for pipelined asynchronous systems. 1191-1196 - Levent Aksoy, Eduardo Costa, Paulo F. Flores, José Monteiro:
Design of low-complexity digital finite impulse response filters on FPGAs. 1197-1202
Modeling of Complex Analogue and Digital Systems
- Zohaib Mahmood, Roberto Suaya, Luca Daniel:
An efficient framework for passive compact dynamical modeling of multiport linear systems. 1203-1208 - Arkosnato Neogy, Jaijeet S. Roychowdhury:
Analysis and design of sub-harmonically injection locked oscillators. 1209-1214 - Peng Gao, Xinpeng Xing, Jan Craninckx, Georges G. E. Gielen:
Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping. 1215-1220 - Wim Schoenmaker, Michael Matthes, Bart De Smedt, Sascha Baumanns, Caren Tischendorf, Rick Janssen:
Large signal simulation of integrated inductors on semi-conducting substrates. 1221-1226
Cyber-Physical Systems
- Dip Goswami, Martin Lukasiewycz, Reinhard Schneider, Samarjit Chakraborty:
Time-triggered implementations of mixed-criticality automotive software. 1227-1232 - Alejandro Masrur, Dip Goswami, Samarjit Chakraborty, Jian-Jia Chen, Anuradha Annaswamy, Ansuman Banerjee:
Timing analysis of cyber-physical applications for hybrid communication protocols. 1233-1238 - Yan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho:
A cyberphysical synthesis approach for error recovery in digital microfluidic biochips. 1239-1244 - Riccardo Muradore, Davide Quaglia, Paolo Fiorini:
Predictive control of networked control systems over differentiated services lossy networks. 1245-1250
On-Line Test and Fault Tolerance
- Ioannis Voyiatzis:
Input vector monitoring on line concurrent BIST based on multilevel decoding logic. 1251-1256 - Kai Du, Peter J. Varman, Kartik Mohanram:
High performance reliable variable latency carry select addition. 1257-1262 - Hsunwei Hsiung, Byeongju Cha, Sandeep K. Gupta:
Salvaging chips with caches beyond repair. 1263-1268 - Kai-Chiang Wu, Ming-Chao Lee, Diana Marculescu, Shih-Chieh Chang:
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms. 1269-1274
Embedded Tutorial - Moore Meets Maxwell
- Raul Camposano, Dipanjan Gope, Stefano Grivet-Talocia, Vikram Jandhyala:
Moore meets maxwell. 1275-1276
Special Day More-Than-Moore: Heterogeneous Integration
- Erik Jan Marinissen:
Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs. 1277-1282
The Quest for NoC Performance
- Radu Andrei Stefan, Anca Mariana Molnos, Jude Angelo Ambrose, Kees Goossens:
A TDM NoC supporting QoS, multicast, and fast connection set-up. 1283-1288 - Shaoteng Liu, Axel Jantsch, Zhonghai Lu:
Parallel probing: Dynamic and constant time setup procedure in circuit switching NoC. 1289-1294 - Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui:
A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels. 1295-1300
Emerging Memory Technologies (1)
- Xiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen, Robinson E. Pino:
Spintronic memristor based temperature sensor design with CMOS current reference. 1301-1306 - Yi Wang, Luis Angel D. Bathen, Zili Shao, Nikil D. Dutt:
3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memory. 1307-1312 - Yaojun Zhang, Xiaobin Wang, Yong Li, Alex K. Jones, Yiran Chen:
Asymmetry of MTJ switching and its implication to STT-RAM designs. 1313-1318
Physical Anchors for Secure Systems
- Geert Jan Schrijen, Vincent van der Leest:
Comparative analysis of SRAM memories used as PUF primitives. 1319-1324 - Abdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet:
Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAs. 1325-1330 - Min Li, Azadeh Davoodi, Mohammad Tehranipoor:
A sensor-assisted self-authentication framework for hardware trojan detection. 1331-1336
Analogue Design Validation
- Henda Aridhi, Mohamed H. Zaki, Sofiène Tahar:
Towards improving simulation of analog circuits using model order reduction. 1337-1342 - Elena I. Vatajelu, Joan Figueras:
Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operation. 1343-1348 - Xuexin Liu, Sheldon X.-D. Tan, Hai Wang, Hao Yu:
A GPU-accelerated envelope-following method for switching power converter simulation. 1349-1354 - Hans Georg Brachtendorf, Kai Bittner, Rainer Laur:
Simulation of the steady state of oscillators in the time domain. 1355-1360
Techniques and Technologies Power Aware Reconfiguration
- Chen Chen, W. Scott Lee, Roozbeh Parsa, Soogine Chong, J. Provine, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra:
Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique. 1361-1366 - Kyuseung Han, Seongsik Park, Kiyoung Choi:
State-based full predication for low power coarse-grained reconfigurable architecture. 1367-1372 - Robin Bonamy, Hung-Manh Pham, Sébastien Pillement, Daniel Chillet:
UPaRC - Ultra-fast power-aware reconfiguration controller. 1373-1378 - Giovanni Mariani, Vlad Mihai Sima, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, Koen Bertels:
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures. 1379-1384
Rise and Fall of Layout
- Ulrich Brenner:
VLSI legalization with minimum perturbation by iterative augmentation. 1385-1390 - Shih-Ying Liu, Chieh-Jui Lee, Hung-Ming Chen:
Agglomerative-based flip-flop merging with signal wirelength optimization. 1391-1396 - Marc Pons, Marc-Nicolas Morgan, Christian Piguet:
Fixed origin corner square inspection layout regularity metric. 1397-1402
Hot Topic - Programmability and Performance Portability of Multi-/Many-Core
- Christoph W. Kessler, Usman Dastgeer, Samuel Thibault, Raymond Namyst, Andrew Richards, Uwe Dolinsky, Siegfried Benkner, Jesper Larsson Träff, Sabri Pllana:
Programmability and performance portability aspects of heterogeneous multi-/manycore systems. 1403-1408
Interactive Presentations
- Yuanzhe Xu, Wenjian Yu, Quan Chen, Lijun Jiang, Ngai Wong:
Efficient variation-aware EM-semiconductor coupled solver for the TSV structures in 3D IC. 1409-1412 - Rajeev Narayanan, Alaeddine Daghar, Mohamed H. Zaki, Sofiène Tahar:
Verifying jitter in an analog and mixed signal design using dynamic time warping. 1413-1416 - Bailey Miller, Frank Vahid, Tony Givargis:
MEDS: Mockup Electronic Data Sheets for automated testing of cyber-physical systems using digital mockups. 1417-1420 - Rédha Hamouche, Rémy Kocik:
Component-based and aspect-oriented methodology and tool for Real-Time Embedded Control Systems Design. 1421-1424 - Christoph M. Kirsch, Eloi Pereira, Raja Sengupta, Hao Chen, Robert Hansen, Jiangchuan Huang, Florian Landolt, Michael Lippautz, Andreas Rottmann, Ryan Swick, Rainer Trummer, D. Vizzini:
Cyber-physical cloud computing: The binding and migration problem. 1425-1428 - Cristiana Bolchini, Antonio Miele, Donatella Sciuto:
An adaptive approach for online fault management in many-core architectures. 1429-1432 - Salvatore Campagna, Massimo Violante:
An hybrid architecture to detect transient faults in microprocessors: An experimental validation. 1433-1438 - Gilles Fritz, Vincent Beroulle, Oum-El-Kheir Aktouf, David Hély:
Evaluation of a new RFID system performance monitoring approach. 1439-1442 - Georgios Panagopoulos, Charles Augustine, Kaushik Roy:
A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach. 1443-1446 - Duo Liu, Tianzheng Wang, Yi Wang, Zhiwei Qin, Zili Shao:
A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems. 1447-1450 - Bo Zhao, Jun Yang, Youtao Zhang, Yiran Chen, Hai Li:
Architecting a common-source-line array for bipolar non-volatile memory devices. 1451-1454 - Sumeet Kumar Gupta, Sang Phill Park, Niladri Narayan Mojumder, Kaushik Roy:
Layout-aware optimization of stt mrams. 1455-1458 - Qingqing Chen, György Csaba, Paolo Lugli, Ulf Schlichtmann, Ulrich Rührmair:
Characterization of the bistable ring PUF. 1459-1462 - Yuanzhe Wang, Haotian Liu, Grantham K. H. Pang, Ngai Wong:
An operational matrix-based algorithm for simulating linear and fractional differential circuits. 1463-1466 - Teo Cupaiuolo, Daniele Lo Iacono:
A flexible and fast software implementation of the FFT on the BPE platform. 1467-1470 - Maximilian Mittag, Andreas Krinke, Göran Jerke, Wolfgang Rosenstiel:
Hierarchical propagation of geometric constraints for full-custom physical design of ICs. 1471-1474 - Islam S. Abed, Amr G. Wassal:
Double-patterning friendly grid-based detailed routing with online conflict resolution. 1475-1478 - Hsin-Pei Tsai, Rung-Bin Lin, Liang-Chi Lai:
Design and analysis of via-configurable routing fabrics for structured ASICs. 1479-1482
Special Day More-Than-Moore: Applications
- Stefan Krone, Bjoern Almeroth, Falko Guderian, Gerhard P. Fettweis:
Towards a wireless medical smart card. 1483-1488
The Frontier of NoC Design
- Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra:
A fast, source-synchronous ring-based network-on-chip design. 1489-1494 - Wei Song, Doug A. Edwards, Jim D. Garside, William J. Bainbridge:
Area efficient asynchronous SDM routers using 2-stage Clos switches. 1495-1500 - Yan Zheng, Peter Lisherness, Ming Gao, Jock Bovington, Shiyuan Yang, Kwang-Ting Cheng:
Power-efficient calibration and reconfiguration for on-chip optical communication. 1501-1506
Emerging Memory Technologies (2)
- Guangyu Sun, Cong Xu, Yuan Xie:
Modeling and design exploration of FBDRAM as on-chip memory. 1507-1512 - Joosung Yun, Sunggu Lee, Sungjoo Yoo:
Bloom filter-based dynamic wear leveling for phase-change RAM. 1513-1518 - Yiqun Wang, Yongpan Liu, Yumeng Liu, Daming Zhang, Shuangchen Li, Baiko Sai, Mei-Fang Chiang, Huazhong Yang:
A compression-based area-efficient recovery architecture for nonvolatile processors. 1519-1524
Digital Communication Systems
- Carlo Condo, Maurizio Martina, Guido Masera:
A Network-on-Chip-based turbo/LDPC decoder architecture. 1525-1530 - Zhibin Yu, C. H. van Berkel, Hong Li:
A complexity adaptive channel estimator for low power. 1531-1536 - Joyce Kwong, Manish Goel:
A high performance split-radix FFT with constant geometry architecture. 1537-1542
Architecture and Networks for Adaptive Computing
- Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne:
Selective flexibility: Breaking the rigidity of datapath merging. 1543-1548 - Mathieu Rosiere, Jean Lou Desbarbieux, Nathalie Drach, Franck Wajsbürt:
An out-of-order superscalar processor on FPGA: The ReOrder Buffer design. 1549-1554 - Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
Partial online-synthesis for mixed-grained reconfigurable architectures. 1555-1560 - Hung-Lin Chao, Yean-Ru Chen, Sheng-Ya Tong, Pao-Ann Hsiung, Sao-Jie Chen:
Congestion-aware scheduling for NoC-based reconfigurable systems. 1561-1566
Boolean Methods in Logic Synthesis
- Kai-Fu Tang, Po-Kai Huang, Chun-Nan Chou, Chung-Yang Huang:
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. 1567-1572 - Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu:
Almost every wire is removable: A modeling and solution for removing any circuit wire. 1573-1578 - Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen:
Mapping into LUT structures. 1579-1584 - Tsutomu Sasao:
Row-shift decompositions for index generation functions. 1585-1590 - Min Li, Azadeh Davoodi, Lin Xie:
Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations. 1591-1596
Impact of Modern Technology on Layout
- Hsin-Wu Hsu, Meng-Ling Chen, Hung-Ming Chen, Hung-Chun Li, Shi-Hao Chen:
On effective flip-chip routing via pseudo single redistribution layer. 1597-1602 - Ayman Yehia Hamouda, Mohab Anis, Karim S. Karim:
AIR (Aerial Image Retargeting): A novel technique for in-fab automatic model-based retargeting-for-yield. 1603-1608 - Matthias Beste, Mehdi Baradaran Tahoori:
Layout-Driven Robustness Analysis for misaligned Carbon Nanotubes in CNTFET-based standard cells. 1609-1614
Embeddded Tutorial - Advances in Variation-Aware Modeling, Verification, and Testing of Analog ICs
- Dimitri de Jonghe, Elie Maricau, Georges G. E. Gielen, Trent McConaghy, Bratislav Tasic, Haralampos-G. D. Stratigopoulos:
Advances in variation-aware modeling, verification, and testing of analog ICs. 1615-1620
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