Xianqing Yao

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Shaojun Wei

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Publications

2018
[j3]
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Shouyi Yin, Tianyi Lu, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei:
Multi-Bank Memory Aware Force Directed Scheduling for High-Level Synthesis. IEEE Access 6: 7526-7540 (2018)
2017
[j2]
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Shouyi Yin, Xianqing Yao, Tianyi Lu, Dajiang Liu, Jiangyuan Gu, Leibo Liu, Shaojun Wei:
Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory. IEEE Trans. Parallel Distributed Syst. 28(9): 2471-2485 (2017)
[c3]
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  - conf/fpga/LuYYXLW17
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Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei:
Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only). FPGA 2017: 290
[c2]
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Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei:
Memory fartitioning-based modulo scheduling for high-level synthesis. ISCAS 2017: 1-4
2016
[j1]
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Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu, Shaojun Wei:
Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24(5): 1895-1908 (2016)
[c1]
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  - conf/iccad/YinYLLW16
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Shouyi Yin, Xianqing Yao, Tianyi Lu, Leibo Liu, Shaojun Wei:
Joint loop mapping and data placement for coarse-grained reconfigurable architecture with multi-bank memory. ICCAD 2016: 127

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