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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 24
Volume 24, Number 1, January 2016
- Nishit Ashok Kapadia, Sudeep Pasricha:
A System-Level Cosynthesis Framework for Power Delivery and On-Chip Data Networks in Application-Specific 3-D ICs. 3-16 - Wei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, Rong-Jyi Yang:
A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM. 17-25 - Mohammadreza Ashraf, Nasser Masoumi:
A Thermal Energy Harvesting Power Supply With an Internal Startup Circuit for Pacemakers. 26-37 - Wei-Sheng Ding, Hung-Yi Hsieh, Cheng-Yu Han, James Chien-Mo Li, Xiaoqing Wen:
Test Pattern Modification for Average IR-Drop Reduction. 38-49 - Tay-Jyi Lin, Ting-Yu Shyu:
Speculative Lookahead for Energy-Efficient Microprocessors. 50-57 - Brian P. Degnan
, Bo Marr, Jennifer Hasler:
Assessing Trends in Performance per Watt for Signal Processing Applications. 58-66 - Jian Wang, Chunlin Xiong, Kangli Zhang, Jibo Wei:
A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT. 67-78 - Qi Guo, Xi Li, Chao Wang, Xuehai Zhou:
Evaluation and Tradeoffs for Out-of-Order Execution on Reconfigurable Heterogeneous MPSoC. 79-91 - Yinhe Han, Jianbo Dong, Kaiheng Weng, Ying Wang, Xiaowei Li:
Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation. 92-102 - Sparsh Mittal, Jeffrey S. Vetter:
EqualWrites: Reducing Intra-Set Write Variations for Enhancing Lifetime of Non-Volatile Caches. 103-114 - Chao Sun, Ayumi Soga, Chihiro Matsui, Asuka Arakawa, Ken Takeuchi:
LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives. 115-128 - Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek, Eby G. Friedman:
Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing. 129-138 - Kejie Huang, Rong Zhao, Wei He, Yong Lian:
High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array. 139-150 - Hamad Marzouqi, Mahmoud Al-Qutayri, Khaled Salah, Dimitrios Schinianakis, Thanos Stouraitis:
A High-Speed FPGA Implementation of an RSD-Based ECC Processor. 151-164 - Mohamed S. Abdelfattah, Vaughn Betz:
Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses. 165-177 - Assem A. M. Bsoul, Steven J. E. Wilton, Kuen Hung Tsoi, Wayne Luk:
An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating. 178-191 - Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta:
PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices. 192-205 - Ioannis Vourkas, Dimitrios Stathis, Georgios Ch. Sirakoulis, Said Hamdioui:
Alternative Architectures Toward Reliable Memristive Crossbar Memories. 206-217 - Mohit Kumar Gupta, Mohd. Hasan:
A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits. 218-222 - Meysam Asghari, Mohammad Yavari:
Using the Gate-Bulk Interaction and a Fundamental Current Injection to Attenuate IM3 and IM2 Currents in RF Transconductors. 223-232 - Neelanjana Pal, Prajit Nandi, Riju Biswas, Ashvinkumar G. Katakwar:
Placement-Based Nonlinearity Reduction Technique for Differential Current-Steering DAC. 233-242 - Yang Xu, Zehong Zhang, Baoyong Chi, Nan Qi, Hualin Cai, Zhihua Wang:
A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ΔΣ ADC With AntiPole-Splitting Opamp and Digital I/Q Calibration. 243-255 - Maryam Zare, Mohammad Maymandi-Nejad:
A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply. 256-265 - Wei Jhih Wang, Chang Hong Lin:
Code Compression for Embedded Systems Using Separated Dictionaries. 266-275 - Jedrzej Kufel, Peter R. Wilson, Stephen Hill, Bashir M. Al-Hashimi, Paul N. Whatmough:
Sequence-Aware Watermark Design for Soft IP Embedded Processors. 276-289 - Chuang Bai, Xuecheng Zou, Kui Dai:
A Novel Thyristor-Based Silicon Physical Unclonable Function. 290-300 - Benjamin Carrión Schäfer:
Source Code Error Detection in High-Level Synthesis Functional Verification. 301-312 - Kamran Rahmani, Sudhi Proch, Prabhat Mishra:
Efficient Selection of Trace and Scan Signals for Post-Silicon Debug. 313-323 - Benjamin Carrión Schäfer:
Tunable Multiprocess Mapping on Coarse-Grain Reconfigurable Architectures With Dynamic Frequency Control. 324-328 - Debajit Bhattacharya, Niraj K. Jha:
TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays. 329-333 - Liang Shi, Yejia Di, Mengying Zhao, Chun Jason Xue, Kaijie Wu, Edwin Hsing-Mean Sha:
Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems. 334-337 - Qingqing Yang, Xiaofang Zhou, Gerald E. Sobelman, Xinxin Li:
Network-on-Chip for Turbo Decoders. 338-342 - Michael Moeng, Haifeng Xu, Rami G. Melhem, Alex K. Jones:
ContextPreRF: Enhancing the Performance and Energy of GPUs With Nonuniform Register Access. 343-347 - Oscal T.-C. Chen, Cheng-Ta Chan, Robin R.-B. Sheen:
Transimpedance Limit Exploration and Inductor-Less Bandwidth Extension for Designing Wideband Amplifiers. 348-352 - Jens Müller, Jan Müller, Robert Braunschweig, Ronald Tetzlaff:
A Cellular Network Architecture With Polynomial Weight Functions. 353-357 - Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish:
Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. 358-362 - Chan-Hui Jeong, Ammar Abdullah, Young-Jae Min, In-Chul Hwang, Soo-Won Kim:
All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications. 363-367 - Kostas Tsoumanis, Sotirios Xydis, Georgios Zervakis, Kiamal Z. Pekmestzi:
Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic. 368-372 - C. B. Kushwah, Santosh Kumar Vishvakarma:
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell. 373-377 - Jesús Moreno, Michel Renovell, Víctor H. Champac:
Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. 378-382 - Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet:
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. 383-387 - Jaeyong Chung, Woochul Kang:
Defect Diagnosis via Segment Delay Learning. 388-392 - Bibhas Ghoshal, Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta:
In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers. 393-397 - Tooraj Nikoubin, Mahdieh Grailoo, Changzhi Li:
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology. 398-402 - Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenhunen:
Polymorphic Configuration Architecture for CGRAs. 403-407 - Ching-Che Chung, Wei-Siang Su, Chi-Kuang Lo:
A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling. 408-412
Volume 24, Number 2, February 2016
- Sumedh Dhabu, Vinod Achutavarrier Prasad:
Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics. 413-420 - Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels. 421-433 - Shiann-Rong Kuang, Kun-Yi Wu, Ren-Yao Lu:
Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication. 434-443 - Basant Kumar Mohanty, Pramod Kumar Meher:
A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications. 444-452 - Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi:
Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching. 453-464 - Masoud Oveis Gharan, Gul N. Khan:
Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems. 465-478 - Evangelia Kasapaki, Martin Schoeberl, Rasmus Bo Sørensen, Christoph Thomas Muller, Kees Goossens, Jens Sparsø:
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation. 479-492 - Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. 493-506 - Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu, Shaojun Wei:
Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures. 507-520 - Pilin Junsangsri, Jie Han, Fabrizio Lombardi:
Logic-in-Memory With a Nonvolatile Programmable Metallization Cell. 521-529 - Juan Antonio Clemente, Ruben Gran, Abel Chocano, Carlos del Prado, Javier Resano:
Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems. 530-543 - Tao Feng, Nizar Lajnef, Shantanu Chakrabartty:
Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry. 544-554 - Wei Wang, James F. Buckwalter:
Source Coding and Preemphasis for Double-Edged Pulsewidth Modulation Serial Communication. 555-566 - Daniel Günther, Rainer Leupers, Gerd Ascheid:
Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing. 567-577 - Shuai Chen, Hao Li, Patrick Yin Chiang:
A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects. 578-586 - Chung-An Shen, Chia-Po Yu, Chien-Hao Huang:
Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes. 587-599 - Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin:
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. 600-612 - Jinhui Wang, Na Gong, Eby G. Friedman:
PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors. 613-624 - Shu-Yung Bin, Shih-Feng Lin, Ya Ching Cheng, Wen-Rong Liau, Alex Hou, Mango C.-T. Chao:
Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics. 625-637 - Mousumi Bhanja, Baidya Nath Ray:
OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application. 638-649 - Morteza Gholipour, Ying-Yu Chen, Amit Sangai, Nasser Masoumi, Deming Chen:
Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis. 650-663 - Qiang Liu, Ming Gao, Qijun Zhang:
Knowledge-Based Neural Network Model for FPGA Logical Architecture Development. 664-677 - Sadia Alam, S. M. Rezaul Hasan:
A VLSI Circuit Emulation of Chemical Synaptic Transmission Dynamics and Postsynaptic DNA Transcription. 678-691 - Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Graph-Based Transistor Network Generation Method for Supergate Design. 692-705 - Chen Hou, Qianchuan Zhao:
A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes. 706-719 - Jun-Ping Wang, Run-Sen Xing, Dan Xu, Yong-Bang Su, Rui-Ping Feng, Rong Wei, Ya-Ning Li, Teng-Wei Zhao:
Redundant Via Insertion Based on SCA. 720-728 - Mehmet Avci, Farid N. Najm:
Verification of the Power and Ground Grids Under General and Hierarchical Constraints. 729-742 - Farhad Alibeygi Parsan, Scott C. Smith, Waleed K. Al-Assadi:
Design for Testability of Sleep Convention Logic. 743-753 - Jihyuck Jo, Hoyoung Yoo, In-Cheol Park:
Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems. 754-758 - Yung-Hsiang Ho, Chia-Yu Yao:
A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register. 759-763 - Jinyoung Kim, Sang-Hoon Park, Hyeokjun Seo, Ki-Whan Song, Sungroh Yoon, Eui-Young Chung:
NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices. 764-768 - Zhen Gao, Pedro Reviriego, Zhan Xu, Xin Su, Ming Zhao, Jing Wang, Juan Antonio Maestro:
Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks. 769-773 - Alexander E. Shapiro, Eby G. Friedman:
Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits. 774-778 - Hao Xiao, Ning Wu, Fen Ge, Tsuyoshi Isshiki, Hiroaki Kunieda, Jun Xu, Yuangang Wang:
Efficient Synchronization for Distributed Embedded Multiprocessors. 779-783 - Tong-Yu Hsieh, Chih-Hao Wang, Tsung-Liang Chih, Ya-Hsiu Chi:
A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies. 784-788 - Yong-Hun Kim, Young-Ju Kim, Taeho Lee, Lee-Sup Kim:
A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method. 789-793 - Si-Nai Kim, Mee-Ran Kim, Ba-Ro-Saim Sung, Hyun-Wook Kang, Min-Hyung Cho, Seung-Tak Ryu:
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm2. 794-798 - Victor Dumitriu, Lev Kirischian:
SoPC Self-Integration Mechanism for Seamless Architecture Adaptation to Stream Workload Variations. 799-802 - Amirreza Alizadeh, Reza Sarvari:
Temperature-Dependent Comparison Between Delay of CNT and Copper Interconnects. 803-807 - M. Hassan Najafi, Mostafa E. Salehi:
A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing. 808-812
Volume 24, Number 3, March 2016
- Pranav S. Vaidya, John Jaehwan Lee, Vijay S. Pai, Miyoung Lee, Sung Jin Hur:
Symbiote Coprocessor Unit - A Streaming Coprocessor for Data Stream Acceleration. 813-826 - Moein Kianpour, Reza Sabbaghi-Nadooshan:
A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM. 827-836 - Osama Ullah Khan, David D. Wentzloff:
Hardware Accelerator for Probabilistic Inference in 65-nm CMOS. 837-845 - Arnab Raha, Hrishikesh Jayakumar, Vijay Raghunathan:
Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding. 846-857 - Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li:
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache. 858-870 - Jongmin Lee, Soontae Kim:
Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems. 871-883 - Mahmoud Zangeneh, Ajay Joshi:
Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization. 884-896 - Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar:
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching. 897-908 - Rabab Ezz-Eldin, Magdy A. El-Moursy, Hesham F. A. Hamed:
Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design. 909-919 - Jintao Zheng, Ning Wu, Lei Zhou, Yunfei Ye, Ke Sun:
DFSB-Based Thermal Management Scheme for 3-D NoC-Bus Architectures. 920-931 - Mojtaba Ebrahimi, Parthasarathy Murali B. Rao, Razi Seyyedi, Mehdi Baradaran Tahoori:
Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames. 932-943 - Seyedhamidreza Motaman, Swaroop Ghosh:
Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches. 944-953 - Mohammad Reza Jokar, Mohammad Arjomand, Hamid Sarbazi-Azad:
Sequoia: A High-Endurance NVM-Based Cache Architecture. 954-967 - Rajiv V. Joshi, Sudesh Saroop, Rouwaida Kanj, Yang Liu, Weike Wang, Carl Radens, Yue Tan, Karthik Yogendra:
A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM. 968-978 - Jianxiao Yang, Benoit Geller, Meng Li, Tong Zhang:
An Information Theory Perspective for the Binary STT-MRAM Cell Operation Channel. 979-991 - Xuanyao Fong, Rangharajan Venkatesan, Dongsoo Lee, Anand Raghunathan, Kaushik Roy:
Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches. 992-1002 - Yasmin Halawani, Baker Mohammad, Dirar Homouz, Mahmoud Al-Qutayri, Hani H. Saleh:
Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications. 1003-1014 - Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung:
All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme. 1015-1024 - Won Namgoong:
An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop. 1025-1035 - Henda Aridhi, Mohamed H. Zaki, Sofiène Tahar:
Enhancing Model Order Reduction for Nonlinear Analog Circuit Simulation. 1036-1049 - Ishita Mukhopadhyay, Mustansir Yunus Mukadam, Rajendran Narayanan, Frank O'Mahony, Alyssa B. Apsel:
Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O. 1050-1058 - Yu Zheng, Fengchao Zhang, Swarup Bhunia:
DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain. 1059-1070 - Seyed Amir Reza Ahmadi Mehr, Massoud Tohidian, Robert Bogdan Staszewski:
Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division. 1071-1082 - Supeng Liu, Yuanjin Zheng:
A Low-Power and Highly Linear 14-bit Parallel Sampling TDC With Power Gating and DEM in 65-nm CMOS. 1083-1091 - Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim:
An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. 1092-1103 - Yu Xia, Kaiming Nie, Jiangtao Xu, Suying Yao:
A Two-Step Analog Accumulator for CMOS TDI Image Sensor With Temporal Undersampling Exposure Method. 1104-1117 - Jebreel M. Salem, Dong Sam Ha:
Dual Use of Power Lines for Design-for-Testability - A CMOS Receiver Design. 1118-1125 - Aoxiang Tang, Niraj K. Jha:
GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis. 1126-1139 - Kai He, Sheldon X.-D. Tan, Hai Wang, Guoyong Shi:
GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis. 1140-1150 - Eric J. Wyers, Matthew A. Morton, T. C. L. Gerhard Sollner, C. T. Kelley, Paul D. Franzon:
A Generally Applicable Calibration Algorithm for Digitally Reconfigurable Self-Healing RFICs. 1151-1164