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ORCIDKazi Asifuzzaman
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2020 – today
- 2025
[c15]Devin Pohl
, Aaron R. Young, Kazi Asifuzzaman, Narasinga Rao Miniskar, Jeffrey S. Vetter:
Mapping Spiking Neural Networks to Heterogeneous Crossbar Architectures using Integer Linear Programming. DATE 2025: 1-7- [c14]Kazi Asifuzzaman, Aaron R. Young, Prasanna Date, Shruti R. Kulkarni, Narasinga Rao Miniskar, Matthew J. Marinella, Jeffrey S. Vetter:
ReSpike: A Co-Design Framework for Evaluating SNNs on ReRAM-Based Neuromorphic Processors. Euro-Par (2) 2025: 175-189 - [c13]Kazi Asifuzzaman, Narasinga Rao Miniskar, William F. Godoy, Oscar R. Hernandez, Jeffrey S. Vetter:
Performance Impact and Trade-Offs for Tuning Key Architectural Parameters on CPU+GPU Systems. GPGPU@PPoPP 2025: 42-47 - [c12]Shamiul Alam, Kazi Asifuzzaman, Ahmedullah Aziz:
UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM. ISVLSI 2025: 1-6 - [i3]Devin Pohl, Aaron R. Young, Kazi Asifuzzaman, Narasinga Rao Miniskar, Jeffrey S. Vetter:
Mapping Spiking Neural Networks to Heterogeneous Crossbar Architectures using Integer Linear Programming. CoRR abs/2503.02033 (2025) - [i2]William F. Godoy, Oscar R. Hernandez, Paul R. C. Kent, Maria Patrou, Kazi Asifuzzaman, Narasinga Rao Miniskar, Pedro Valero-Lara, Jeffrey S. Vetter, Matthew D. Sinclair, Jason Lowe-Power, Bobby R. Bruce:
Characterizing GPU Energy Usage in Exascale-Ready Portable Science Applications. CoRR abs/2505.05623 (2025) - 2024
- [j2]Shamiul Alam, Jack Hutchins, Nikhil Shukla, Kazi Asifuzzaman, Ahmedullah Aziz:
CMOS-Based Single-Cycle in-Memory XOR/XNOR. IEEE Access 12: 49528-49534 (2024) - [c11]Narasinga Rao Miniskar, Aaron R. Young, Kazi Asifuzzaman, Shruti R. Kulkarni, Prasanna Date, Alice Bean, Jeffrey S. Vetter:
Neuro-Spark: A Submicrosecond Spiking Neural Networks Architecture for In-Sensor Filtering. ICONS 2024: 63-70 - 2023
- [c10]Shamiul Alam, Kazi Asifuzzaman, Ahmedullah Aziz:
A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths. ISQED 2023: 1-7 - [i1]Shamiul Alam, Jack Hutchins, Nikhil Shukla, Kazi Asifuzzaman, Ahmedullah Aziz:
CMOS-based Single-Cycle In-Memory XOR/XNOR. CoRR abs/2310.18375 (2023) - 2022
- [j1]Kazi Asifuzzaman, Rommel Sánchez Verdejo, Petar Radojkovic:
Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation. ACM Trans. Embed. Comput. Syst. 21(1): 6:1-6:25 (2022) - [c9]Kazi Asifuzzaman, Mohammad Alaul Haque Monil, Frank Liu, Jeffrey S. Vetter:
Evaluating HPC Kernels for Processing in Memory. MEMSYS 2022: 1:1-1:6 - 2021
- [c8]Alvaro Jover-Alvarez, Alejandro J. Calderón, Iván Rodriguez, Leonidas Kosmidis, Kazi Asifuzzaman, Patrick Uven, Kim Grüttner, Tomaso Poggi, Irune Agirre:
The UP2DATE Baseline Research Platforms. DATE 2021: 1340-1343 - [c7]Kazi Asifuzzaman, Mohamed Abuelala, Mohamed Hassan, Francisco J. Cazorla:
Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems. ICCAD 2021: 1-9
2010 – 2019
- 2019
- [b1]Kazi Asifuzzaman:
Evaluation of STT-MRAM main memory for HPC and real-time systems. Polytechnic University of Catalonia, Spain, 2019 - [c6]Kazi Asifuzzaman, Mikel Fernández, Petar Radojkovic, Jaume Abella, Francisco J. Cazorla:
STT-MRAM for real-time embedded systems: performance and WCET implications. MEMSYS 2019: 195-205 - 2018
- [c5]Milan Radulovic, Kazi Asifuzzaman, Paul M. Carpenter, Petar Radojkovic, Eduard Ayguadé:
HPC Benchmarking: Scaling Right and Looking Beyond the Average. Euro-Par 2018: 135-146 - [c4]Rommel Sánchez Verdejo, Kazi Asifuzzaman, Milan Radulovic, Petar Radojkovic, Eduard Ayguadé, Bruce L. Jacob:
Main memory latency simulation: the missing link. MEMSYS 2018: 107-116 - [c3]Milan Radulovic, Kazi Asifuzzaman, Darko Zivanovic, Nikola Rajovic, Guillaume Colin de Verdière, Dirk Pleiter, Manolis Marazakis, Nikolaos D. Kallimanis, Paul M. Carpenter, Petar Radojkovic, Eduard Ayguadé:
Mainstream vs. Emerging HPC: Metrics, Trade-Offs and Lessons Learned. SBAC-PAD 2018: 250-257 - 2017
- [c2]Kazi Asifuzzaman, Rommel Sánchez Verdejo, Petar Radojkovic:
Enabling a reliable STT-MRAM main memory simulation. MEMSYS 2017: 283-292 - 2016
- [c1]Kazi Asifuzzaman, Milan Pavlovic, Milan Radulovic, David Zaragoza, Ohseong Kwon, Kyung-Chang Ryoo, Petar Radojkovic:
Performance Impact of a Slower Main Memory: A case study of STT-MRAM in HPC. MEMSYS 2016: 40-49
Coauthor Index
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