default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID24th ISQED 2023: San Francisco, CA, USA
- 24th International Symposium on Quality Electronic Design, ISQED 2023, San Francisco, CA, USA, April 5-7, 2023. IEEE 2023, ISBN 979-8-3503-3475-3
- Ning-Chi Huang, Min-Syue Yang, Ya-Chu Chang, Kai-Chiang Wu:
Decomposable Architecture and Fault Mitigation Methodology for Deep Learning Accelerators. 1-8 - Juneet Kumar Meka, Ranga Vemuri:
Attributed Graph Transformation for Generating Synthetic Benchmarks for Hardware Security. 1-9 - Madhava Sarma Vemuri
, Umamaheswara Rao Tida:
Metal Inter-layer Via Keep-out-zone in M3D IC: A Critical Process-aware Design Consideration. 1-8 - Qazi Arbab Ahmed, Muhammad Awais, Marco Platzner:
MAAS: Hiding Trojans in Approximate Circuits. 1-6 - Jun Yin, Mircea R. Stan:
A Low Power SRAM with Fully Dynamic Leakage Suppression for IoT Nodes. 1-8 - Po-Yang Chen, Chang-Yun Liu, Hung-Ming Chen, Po-Tsang Huang:
On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC. 1-6 - Gabriel Barajas, Jonathan W. Greene, Fei Li, James Tandon:
Accounting for Floorplan Irregularity and Configuration Dependence in FPGA Routing Delay Models. 1-6 - Karl Ott, Rabi N. Mahapatra:
Hardware Performance Counter Enhanced Watchdog for Embedded Software Security. 1-8 - Deepraj Soni, Mohammed Nabeel, Homer Gamil, Oleg Mazonka, Brandon Reagen, Ramesh Karri, Michail Maniatakos:
Design Space Exploration of Modular Multipliers for ASIC FHE accelerators. 1-8 - Kwondo Ma, Chandramouli N. Amarnath, Abhijit Chatterjee, Jacob A. Abraham:
Secure Control Loop Execution of Cyber-Physical Devices Using Predictive State Space Checks. 1-8 - Sairam Sri Vatsavai, Venkata Sai Praneeth Karempudi, Ishan G. Thakkar:
An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks. 1-8 - Partha Sarathi Paul, Maisha Sadia, Anurag Dhungel, Parker Hardy, Md Sakib Hasan:
Split-Slope Chaotic Map Providing High Entropy Across Wide Range. 1-6 - Vishesh Mishra, Sparsh Mittal, Rekha Singhal, Manoj Nambiar:
Novel, Configurable Approximate Floating-point Multipliers for Error-Resilient Applications. 1-7 - Sairam Sri Vatsavai, Ishan G. Thakkar:
A Bit-Parallel Deterministic Stochastic Multiplier. 1 - Luke R. Upton, Guénolé Lallement, Michael D. Scott, Joyce Taylor, Robert M. Radway, Dennis Rich, Mark Nelson, Subhasish Mitra, Boris Murmann:
Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices. 1-7 - Patricia Gonzalez-Guerrero, Kylie Huch, Nirmalendu Patra, Doru-Thom Popovici, George Michelogiannakis:
An Area Efficient Superconducting Unary CNN Accelerator. 1-8 - Chia-Heng Yen, Jung-Che Tsai, Kai-Chiang Wu:
Using Path Features for Hardware Trojan Detection Based on Machine Learning Techniques. 1-8 - Supreeth Mysore Shivanandamurthy, Sairam Sri Vatsavai, Ishan G. Thakkar, Sayed Ahmad Salehi:
AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning. 1-8 - Mengxin Zheng, Fan Chen, Lei Jiang, Qian Lou:
PriML: An Electro-Optical Accelerator for Private Machine Learning on Encrypted Data. 1-7 - Sourav Roy, Shahin Tajik, Domenic Forte:
Polymorphic Sensor to Detect Laser Logic State Imaging Attack. 1-8 - Shiya Liu, Yang Yi:
Knowledge Distillation between DNN and SNN for Intelligent Sensing Systems on Loihi Chip. 1-8 - Mayank Kabra, Prashanth H. C., Kedar Deshpande, Madhav Rao:
eDRAM-OESP: A novel performance efficient in-embedded-DRAM-compute design for on-edge signal processing application. 1-7 - Md. Omar Faruque, Wenjie Che:
Enlarging Reliable Pairs via Inter-Distance Offset for a PUF Entropy-Boosting Algorithm. 1-8 - Bikrant Das Sharma, Abdul Rahman Ismail, Chris Meyers:
Power Savings in USB Hubs Through A Proactive Scheduling Strategy. 1-7 - Yueqin Dai, Yifeng Song, Jing Tian, Zhongfeng Wang:
High-Throughput Hardware Implementation for Haraka in SPHINCS+. 1-6 - Yash Khare, Kumud Lakara, Sparsh Mittal, Arvind Kaushik, Rekha Singhal:
SpotOn: A Gradient-based Targeted Data Poisoning Attack on Deep Neural Networks. 1-8 - Esther Roorda, Steven J. E. Wilton:
Online Training from Streaming Data with Concept Drift on FPGAs. 1-8 - Ya-sine Agrignan, Shanglin Zhou, Jun Bai, Sahidul Islam, Sheida Nabavi, Mimi Xie, Caiwen Ding:
A Deep Learning Approach for Ventricular Arrhythmias Classification using Microcontroller. 1-5 - Shamiul Alam, Kazi Asifuzzaman, Ahmedullah Aziz:
A Novel Scalable Array Design for III-V Compound Semiconductor-based Nonvolatile Memory (UltraRAM) with Separate Read-Write Paths. 1-7 - Nishant Bharti, Arijit Nath, Swati Upadhyay, Hemangee K. Kapoor:
ZOCHEN: Compression Using Zero Chain Elimination and Encoding to Improve Endurance of Non-Volatile Memories. 1-8 - Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Shairfe Muhammad Salahuddin, Francky Catthoor, Zsolt Tokei, Chenyun Pan:
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access. 1 - Noah Zins, Hongyu An:
Reproducing Fear Conditioning of Rats with Unmanned Ground Vehicles and Neuromorphic Systems. 1-7 - Ankit Shukla, Laura Heller, Md Golam Morshed, Laura Rehm, Avik W. Ghosh, Andrew D. Kent, Shaloo Rakheja:
A True Random Number Generator for Probabilistic Computing using Stochastic Magnetic Actuated Random Transducer Devices. 1-10 - Pengzhou He, Jiafeng Xie:
Novel Implementation of High-Performance Polynomial Multiplication for Unified KEM Saber based on TMVP Design Strategy. 1-8 - Mehrdad Morsali, Ranyang Zhou, Sepehr Tabrizchi, Arman Roohi, Shaahin Angizi:
XOR-CiM: An Efficient Computing-in-SOT-MRAM Design for Binary Neural Network Acceleration. 1-5 - Mohamed El-Hadedy, Russell Hua, Kazutomo Yoshii, Wen-Mei Hwu, Martin Margala:
RECO-LFSR: Reconfigurable Low-power Cryptographic processor based on LFSR for Trusted IoT platforms. 1-7 - Richard C. Yarnell, Mousam Hossain, Ronald F. DeMara:
Image Quantization Tradeoffs in a YOLO-based FPGA Accelerator Framework. 1-7 - Xinyuan Qiao, Suwen Song, Jing Tian, Zhongfeng Wang:
Efficient Decryption Architecture for Classic McEliece. 1-7 - Honghao Zheng, Yang Yi:
Spiking Domain Feature Extraction with Temporal Dynamic Learning. 1-5 - Dhanasekar V, Vinodhini Gunasekaran, Anusha Challa, Bama Srinivasan, J. Dhurga Devi, Selvi Ravindran, Ranjani Parthasarathi, P. V. Ramakrishna, Gopika Geetha Kumar, Venkateswaran Padmanabhan, Guha Lakshmanan, Lakshmanan Balasubramanian:
Analysis of Machine Learning Techniques for Time Domain Waveform Prediction in Analog and Mixed Signal Integrated Circuit Verification. 1-9 - Chieh-Yu Cheng, Ting-Chi Wang:
Routability-aware Placement Guidance Generation for Mixed-size Designs. 1-7 - Man Shi, Steven Colleman, Charlotte VanDeMieroop, Antony Joseph, Maurice Meijer, Wim Dehaene, Marian Verhelst:
CMDS: Cross-layer Dataflow Optimization for DNN Accelerators Exploiting Multi-bank Memories. 1-8 - Nastaran Darabi, Maeesha Binte Hashem, Supriyo Bandyopadhyay, Amit Ranjan Trivedi:
Exploiting Programmable Dipole Interaction in Straintronic Nanomagnet Chains for Ising Problems. 1 - Tianqi Zhang, Sahand Salamat, Behnam Khaleghi, Justin Morris, Baris Aksanli, Tajana Simunic Rosing:
HD2FPGA: Automated Framework for Accelerating Hyperdimensional Computing on FPGAs. 1-9 - Sandeep Koranne:
Design of Hardware Accelerators to Compute Parametric Capacitance Tables. 1-8 - Garret Cunningham, Harsha Chenji, David Juedes, Gordon Stewart, Avinash Karanth:
DAGGER: Exploiting Language Semantics for Program Security in Embedded Systems. 1-7 - Shailesh Rajput, Jaya Dofe, Wafi Danesh:
Automating Hardware Trojan Detection Using Unsupervised Learning: A Case Study of FPGA. 1-6 - Zihao Chen, Songlei Meng, Fan Yang, Li Shang, Xuan Zeng:
TOTAL: Topology Optimization of Operational Amplifier via Reinforcement Learning. 1-8 - Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, Rolf Drechsler:
VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking. 1-8 - Sathwika Bavikadi, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao:
Heterogeneous Multi-Functional Look-Up-Table-based Processing-in-Memory Architecture for Deep Learning Acceleration. 1-8 - Brendan Reidy, David Duggan, Bernard Glasauer, Peng Su, Ramtin Zand:
Application of Machine Learning for Quality Risk Factor Analysis of Electronic Assemblies. 1-6 - MinSeok Han, Jiwan Kim, Donggeon Kim, Hyunuk Jeong, Gilho Jung, Myeongwon Oh, Hyundong Lee, Yunjeong Go, HyunWoo Kim, Jongbeom Kim, Taigon Song:
HFGCN: High-speed and Fully-optimized GCN Accelerator. 1-7 - Simon Friedrich, Shambhavi Balamuthu Sampath, Robert Wittig, Manoj Rohit Vemparala, Nael Fasfous, Emil Matús, Walter Stechele, Gerhard P. Fettweis:
Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands. 1-8 - Daniel Xing, Michael Zuzak, Ankur Srivastava:
Low Overhead System-Level Obfuscation through Hardware Resource Sharing. 1-8 - Robert Viramontes, Azadeh Davoodi:
Neural Network Partitioning for Fast Distributed Inference. 1-7 - Joseph Lindsay, Ramtin Zand:
A Novel Stochastic LSTM Model Inspired by Quantum Machine Learning. 1-8 - Arun Govindankutty, Shamiul Alam, Sanjay Das, Ahmedullah Aziz, Sumitha George:
Cryogenic In-memory Binary Multiplier Using Quantum Anomalous Hall Effect Memories. 1-7 - Dake Chen, Xuan Zhou, Yinghua Hu, Yuke Zhang, Kaixin Yang, Andrew Rittenbach, Pierluigi Nuzzo, Peter A. Beerel:
Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILP. 1-8 - Ruben Dominguez, Wen Zhang, Hongzhi Xu, Pablo Rangel, Chen Pan:
ISSAC: An Self-organizing and Self-healing MAC Design for Intermittent Communication Systems. 1-8 - Zhangying He, Hossein Sayadi:
Image-Based Zero-Day Malware Detection in IoMT Devices: A Hybrid AI-Enabled Method. 1-8 - Wei Zhou, Aijiao Cui, Cassi Chen, Gang Qu:
A Low-overhead PUF-based Secure Scan Design. 1-6 - Andrew B. Kahng, Shreyas Thumathy, Mingyu Woo:
An Effective Cost-Skew Tradeoff Heuristic for VLSI Global Routing. 1-8 - Md. Mazharul Islam, Md. Shafayat Hossain, Ahmedullah Aziz:
A SPICE-based Framework to Emulate Quantum Circuits with classical LC Resonators. 1-7 - Kangjun Bai, Daniel Titcombe, Jack Lombardi, Clare Thiem, Nathaniel C. Cady:
Moving Towards Game-Changing Technology: Fabrication and Application of HfO2 RRAM for In-Memory Computing. 1-7 - Mahdi Taheri, Mohammad Riazati, Mohammad Hasan Ahmadilivani, Maksim Jenihhin, Masoud Daneshtalab, Jaan Raik, Mikael Sjödin, Björn Lisper:
DeepAxe: A Framework for Exploration of Approximation and Reliability Trade-offs in DNN Accelerators. 1-8 - Zhenyi Gao, Sheqin Dong, Zhicong Tang, Wenjian Yu:
MC-MCF: A Multi-Capacity Model for Ordered Escape Routing. 1-7 - Rahul Vishwakarma, Ravi Monani, Amin Rezaei, Hossein Sayadi, Mehrdad Aliasgari, Ava Hedayatipour:
Attacks on Continuous Chaos Communication and Remedies for Resource Limited Devices. 1-8 - Andrea Guerrieri, Gabriel Da Silva Marques, Francesco Regazzoni, Andres Upegui:
H-Saber: An FPGA-Optimized Version for Designing Fast and Efficient Post-Quantum Cryptography Hardware Accelerators. 1-6 - Brady Prince, M. Hassan Najafi, Bingzhe Li:
Scalable Low-Cost Sorting Network with Weighted Bit-Streams. 1-6 - Quanbao Guo, Keni Qiu:
A2OP: an A* Algorithm OPtimizer with the Heuristic Function for PCB Automatic Routing. 1 - Zhiyao Xie, Tao Zhang, Yifeng Peng:
Security and Reliability Challenges in Machine Learning for EDA: Latest Advances. 1-6 - Ashvinikumar Dongre, Gaurav Trivedi:
Binary Synaptic Array for Inference and Training with Built-in RRAM Electroforming Circuit. 1-6 - Shih-Jung Pao, Chuan-Pin Huang, Yen-Chi Peng, Ing-Jer Huang:
Focusing on the Key Suspicious Trojan Nets with a Collaborative Approach. 1-8 - Joseph Clemmons, Yu-Fang Jin:
Reinforcement Learning-Based Guidance of Autonomous Vehicles. 1-6 - Jaspinder Kaur, Shirshendu Das:
ACPC: Covert Channel Attack on Last Level Cache using Dynamic Cache Partitioning. 1-8 - Archie Mishra, Nanditha Rao:
DSEAdd: FPGA based Design Space Exploration for Approximate Adders with Variable Bit-precision. 1-8 - Yuan Wang, Jian Xin, Haixu Liu, Qian Qin, Chenkai Chai, Yukai Lu, Jinglei Hao, Jianhao Xiao, Zuochang Ye, Yan Wang:
DC-Model: A New Method for Assisting the Analog Circuit Optimization. 1-7 - Yuqin Dou, Chongyan Gu, Chenghua Wang, Weiqiang Liu:
A Novel Method Against Hardware Trojans in Approximate Circuits. 1-6 - Jordan Maynard, Amin Rezaei:
DK Lock: Dual Key Logic Locking Against Oracle-Guided Attacks. 1-7 - N. S. Aswathy, Hemangee K. Kapoor:
AGRAS: Aging and memory request rate aware scheduler for PCM memories. 1-8 - Mayank Kabra, Prashanth H. C., Kedar Deshpande, Madhav Rao:
HIE-DRAM: High Performance Efficient In-DRAM Computing Architecture for SIMD. 1-7 - Bijan Shahriari, Farid N. Najm:
Fast Electromigration Simulation for Chip Power Grids. 1-8 - Omari Paul, Sakib Abrar, Richard Mu, Riadul Islam, Manar D. Samad:
Deep Image Segmentation for Defect Detection in Photo-lithography Fabrication. 1-7 - Ram Venkat Narayanan, Aparajithan Nathamuni Venkatesan, Kishore Pula, Sundarakumar Muthukumaran, Ranga Vemuri:
Reverse Engineering Word-Level Models from Look-Up Table Netlists. 1-8 - James Geist, Travis Meade, Shaojie Zhang, Yier Jin:
NetViz: A Tool for Netlist Security Visualization. 1-8 - Hsin-Ping Yen, Shiuan-Hau Huang, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang:
A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation. 1-8 - Bindu G. Gowda, Prashanth H. C., Madhav Rao:
Error Diluted Approximate Multipliers Using Positive And Negative Compressors. 1-7 - Prashanth H. C., Sriniketh S. S, Shrikrishna Hebbar, Chinmaye R, Madhav Rao:
SQRTLIB : Library of Hardware Square Root Designs. 1-5 - Rakibul Hassan, Charan Bandi, Meng-Tien Tsai, Shahriar Golchin, Sai Manoj P. D., Setareh Rafatirad, Soheil Salehi:
Automated Supervised Topic Modeling Framework for Hardware Weaknesses. 1-8 - Zigeng Wang, Bingbing Li, Xia Xiao, Tianyun Zhang, Mikhail A. Bragin, Bing Yan, Caiwen Ding, Sanguthevar Rajasekaran:
Automatic Subnetwork Search Through Dynamic Differentiable Neuron Pruning. 1-6 - Venkata Sai Praneeth Karempudi, Sairam Sri Vatsavai, Ishan G. Thakkar, Jeffrey Todd Hastings:
A Polymorphic Electro-Optic Logic Gate for High-Speed Reconfigurable Computing Circuits. 1-8 - Harshita Gupta, Mayank Kabra, Nitin D. Patwari, Prashanth H. C., Madhav Rao:
Design and Evaluation of multipliers for hardware accelerated on-chip EdDSA. 1-9 - Hyunwoo Kim, Hyundong Lee, Jongbeom Kim, Yunjeong Go, Seungwon Baek, Jaehong Song, Junhyeon Kim, Minyoung Jung, Hyodong Kim, Seongju Kim, Taigon Song:
Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory. 1-6 - P. R. Chithira:
Accurate Estimation of Circuit Delay Variance with Limited Monte Carlo Simulations Using Bayesian Inference. 1-6 - Cheng-Yen Lee, Sunil P. Khatri, Sarma B. K. Vrudhula:
A Novel Pseudo-Flash Based Digital Low Dropout (LDO) Voltage Regulator. 1-7 - Ananya Mantravadi, Dhruv Makwana, R. Sai Chandra Teja, Sparsh Mittal, Rekha Singhal:
Dilated Involutional Pyramid Network (DInPNet): A Novel Model for Printed Circuit Board (PCB) Components Classification. 1-7 - Sekhar Reddy Kola, Yiming Li, Min-Hui Chuang:
Intrinsic Parameter Fluctuation and Process Variation Effect of Vertically Stacked Silicon Nanosheet Complementary Field-Effect Transistors. 1-8 - Lakshmi Sathidevi, Abhinav Sharma, Nan Wu, Xun Jiao, Cong Hao:
PreAxC: Error Distribution Prediction for Approximate Computing Quality Control using Graph Neural Networks. 1-7 - Xiaotian Ma, Jiaqi Tang, Yu Bai:
Locality-sensing Fast Neural Network (LFNN): An Efficient Neural Network Acceleration Framework via Locality Sensing for Real-time Videos Queries. 1-8 - Prokash Ghosh, V. N. Dwaraka Mai, Aditya Chopra, Baljinder Sood:
Self-Checking Performance Verification Methodology for Complex SoCs. 1-8 - Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler:
Polynomial Formal Verification of a Processor: A RISC-V Case Study. 1-7 - Tasnuva Farheen, Shahin Tajik, Domenic Forte:
SPRED: Spatially Distributed Laser Fault Injection Resilient Design. 1-8 - Vidya A. Chhabria, Sachin S. Sapatnekar:
Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design. 1-7 - Vandana Kumari, Maya Chandrakar, Manoj Kumar Majumder:
Performance Analysis of Cylindrical Through Silicon Via with Interfacial Crack. 1-6 - Felipe Almeida, Levent Aksoy, Quang-Linh Nguyen, Sophie Dupuis, Marie-Lise Flottes, Samuel Pagliarini:
Resynthesis-based Attacks Against Logic Locking. 1-8 - Shalabh Jain, Pradeep Pappachan, Jorge Guajardo, Sven Trieflinger, Indrasen Raghupatruni, Thomas Huber:
CMP-SiL: Confidential Multi Party Software-in-the-Loop Simulation Frameworks. 1-8 - Xiangyun Wang, Yicheng Song, Katyayani Prakash, Zeljko Zilic, Tomas Langsetmo:
Quality-driven Design Methodology for PUFs in FPGAs for Secure IoT. 1-8
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-28 23:52 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
