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Journal Articles
- 2010
[j2]Ke-Chung Wu, Jri Lee:
A 2 , ˟, 25-Gb/s Receiver With 2: 5 DMUX for 100-Gb/s Ethernet. IEEE J. Solid State Circuits 45(11): 2421-2432 (2010)- 2009
- [j1]Jri Lee, Ke-Chung Wu:
A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition. IEEE J. Solid State Circuits 44(12): 3590-3602 (2009)
Conference and Workshop Papers
- 2019
- [c3]Tamer A. Ali, Ramy Yousry, Henry Park, Ehung Chen, Po-Shuan Weng, Yi-Chieh Huang, Chun-Cheng Liu, Chien-Hua Wu, Shih-Hao Huang, Chungshi Lin, Ke-Chung Wu, Kun-Hung Tsai, Kai-Wen Tan, Ahmed ElShater, Kuang-Ren Chen, Wei-Hao Tsai, Huan-Sheng Chen, Weiyu Leng, Mazen Soliman:
A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology. ISSCC 2019: 118-120 - 2010
- [c2]Ke-Chung Wu, Jri Lee:
A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications. ISSCC 2010: 374-375 - 2009
- [c1]Jri Lee, Ke-Chung Wu:
A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition. ISSCC 2009: 366-367
Coauthor Index
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