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ORCIDIEEE Journal of Solid-State Circuits, Volume 45
Volume 45, Number 1, January 2010
- Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
A 45 nm 8-Core Enterprise Xeon¯ Processor. 7-14 - Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno:
A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors. 15-22 - Carlos Tokunaga, David T. Blaauw:
Securing Encryption Systems With a Switched Capacitor Current Equalizer. 23-31 - Joo-Young Kim, Minsu Kim, Seungjin Lee, Jinwook Oh, Kwanho Kim, Hoi-Jun Yoo:
A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine. 32-45 - Li-Fu Ding, Wei-Yin Chen, Pei-Kuei Tsung, Tzu-Der Chuang, Pai-Heng Hsiao, Yu-Han Chen, Hsu-Kuang Chiu, Shao-Yi Chien
, Liang-Gee Chen:
A 212 MPixels/s 4096 ˟ 2160p Multiview Video Encoder Chip for 3D/Quad Full HDTV Applications. 46-58 - Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori:
A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits. 59-68 - Nick Van Helleputte, Marian Verhelst, Wim Dehaene, Georges G. E. Gielen:
A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging. 69-83 - Pierre Busson, Nitin Chawla, Jérôme Bach, Stéphane Le Tual, Harvinder Singh, Vineet Gupta, Pascal Urard:
A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit. 84-94 - Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar:
A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. 95-102 - Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr:
A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. 103-110 - Uksong Kang, Hoeju Chung, Seongmoo Heo, Dukha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam-Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo-Sun Choi, Changhyun Kim, Young-Hyun Jun:
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. 111-119 - Rex Kho, David Boursin, Martin Brox, Peter Gregorius, Heinz Hoenigschmid, Bianka Kho, Sabine Kieser, Daniel Kehrer, Maksim Kuzmenka, Udo Moeller, Pavel Veselinov Petkov, Manfred Plan, Michael Richter, Ian Russell, Kai Schiller, Ronny Schneider, Kartik Swaminathan, Bradley Weber, Julien Weber, Ingo Bormann, Fabien Funfrock, Mario Gjukic, Wolfgang Spirkl, Holger Steffens, Jörg Weller, Thomas Hein:
A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques. 120-133 - Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. 134-141 - Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko M. Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama:
A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes. 142-152 - Denis C. Daly, Patrick P. Mercier, Manish Bhardwaj, Alice L. Stone, Zane N. Aldworth, Thomas L. Daniel, Joel Voldman, John G. Hildebrand, Anantha P. Chandrakasan:
A Pulsed UWB Receiver SoC for Insect Motion Control. 153-166 - Martin Flatscher, Markus Dielacher, Thomas Herndl, Thomas Lentsch, Rainer Matischek, Josef Prainsack, Wolfgang Pribyl, Horst Theuss, Werner Weber:
A Bulk Acoustic Wave (BAW) Based Transceiver for an In-Tire-Pressure Monitoring Sensor Node. 167-177 - Jerald Yoo, Long Yan, Seulki Lee, Yongsang Kim, Hoi-Jun Yoo:
A 5.2 mW Self-Configured Wearable Body Sensor Network Controller and a 12 μ W Wirelessly Powered Sensor for a Continuous Health Monitoring System. 178-188 - Yogesh K. Ramadass, Anantha P. Chandrakasan:
An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Bias-Flip Rectifier and Shared Inductor. 189-204 - Mirko Frank, Matthias Kuhl, Gilbert Erdler, Ingo Freund, Yiannos Manoli, Claas Müller, Holger Reinecke:
An Integrated Power Supply System for Low Power 3.3 V Electronics Using On-Chip Polymer Electrolyte Membrane (PEM) Fuel Cells. 205-213 - Patrick Villard, Ursula Ebels, Dimitri Houssameddine, Jordan A. Katine, Daniele Mauri, Bertrand Delaet, Pierre Vincent, Marie Claire Cyrille, Bernard Viala, Jean-Philippe Michel, Jérôme Prouvée, Franck Badets:
A GHz Spintronic-Based RF Oscillator. 214-223 - David Ruffieux, François Krummenacher, Aurélie Pezous, Guido Spinola-Durante:
Silicon Resonator Based 3.2 muW Real Time Clock With pm10 ppm Frequency Accuracy. 224-234 - Ian A. Young, Edris Mohammed, Jason T. S. Liao, Alexandra M. Kern, Samuel Palermo, Bruce A. Block, Miriam R. Reshotko, Peter L. D. Chang:
Optical I/O Technology for Tera-Scale Computing. 235-248 - Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai:
Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection. 249-259
Volume 45, Number 2, February 2010
- Jri Lee, Yentso Chen, Yenlin Huang:
A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly. 264-275 - Roman Staszewski, Robert Bogdan Staszewski, Tom Jung, Thomas Murphy, Imran Bashir, Oren E. Eliezer, Khurram Muhammad, Mitch Entezari:
Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS. 276-288 - Mohamed El-Nozahi, Edgar Sánchez-Sinencio, Kamran Entesari:
A Millimeter-Wave (23-32 GHz) Wideband BiCMOS Low-Noise Amplifier. 289-299 - Xueyang Geng, Fa Foster Dai, J. David Irwin, Richard C. Jaeger:
An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC. 300-313 - Wei Liu, Wei (Ruth) Li, Peng Ren, Chinglong Lin, Shengdong Zhang, Yangyuan Wang:
A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO. 314-321 - Nelson Lam, Bosco H. Leung:
Dynamic Quadrant Swapping Scheme Implemented in a Post Conversion Block for I, Q Mismatch Reduction in a DQPSK Receiver. 322-337 - Horng-Yuan Shih, Chien-Nan Kuo, Wei-Hsien Chen, Tzu-Yi Yang, Kai-Chenug Juang:
A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband. 338-350 - Mohamed Mobarak, Marvin Onabajo, José Silva-Martínez, Edgar Sánchez-Sinencio:
Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications. 351-367 - Yun-Shiang Shu, Junpei Kamiishi, Koji Tomioka, Koichi Hamashita, Bang-Sup Song:
LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators. 368-379 - Michael Chu, Philip Jacob, Jin Woo Kim, Mitchell R. LeRoy, Russell P. Kraft, John F. McDonald:
A 40 Gs/s Time Interleaved ADC Using SiGe BiCMOS Technology. 380-390 - Charles T. Peach, Un-Ku Moon, David J. Allstot:
An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 μ m CMOS. 391-400 - Ik Joon Chang, Sang Phill Park, Kaushik Roy:
Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation. 401-410 - Chun-Hao Liao, To-Ping Wang, Tzi-Dar Chiueh:
A 74.8 mW Soft-Output Detector IC for 8 , ˟, 8 Spatial-Multiplexing MIMO Communications. 411-421 - Cheng-Chi Wong, Ming-Wei Lai, Chien-Ching Lin, Hsie-Chia Chang, Chen-Yi Lee:
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture. 422-432 - Jian-Hao Lu, Shen-Iuan Liu:
A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers. 433-446 - Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects. 447-457 - Pui Ying Or, Ka Nang Leung:
An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection. 458-466 - Urs Frey, Jan Sedivý, Flavio Heer, René Pedron, Marco Ballini, Jan Mueller, Douglas J. Bakkum, Sadik Hafizovic, Francesca D. Faraci, Frauke Greve, Kay-Uwe Kirstein, Andreas Hierlemann:
Switch-Matrix-Based High-Density Microelectrode Array in CMOS Technology. 467-482 - Erick O. Torres, Gabriel A. Rincón-Mora:
A 0.7- μ m BiCMOS Electrostatic Energy-Harvesting System IC. 483-496 - Kwang-Il Oh, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Joo-Sun Choi, Kinam Kim:
Correction on "A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme" [Aug 09 2222-2232]. 497 - Barbara Baggini, Philipp Basedau, Rolf Becker, Peter Bode, Farzad Esfahani, Willem H. Groeneweg, Markus Helfenstein, Alexander Lampe, Roland Ryter, Ralph Stephan:
Correction to "Baseband and Audio Mixed-Signal Front-End IC for GSM/EDGE Applications" [Jun 06 1364-1379]. 498
Volume 45, Number 3, March 2010
- Yueh-Hua Yu, Yong-Sian Yang, Yi-Jan Emery Chen:
A Compact Wideband CMOS Low Noise Amplifier With Gain Flatness Enhancement. 502-509 - Kuang-Wei Cheng, Karthik Natarajan, David J. Allstot:
A Current Reuse Quadrature GPS Receiver in 0.13 μ m CMOS. 510-523 - Masum Hossain, Anthony Chan Carusone:
5-10 Gb/s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS. 524-537 - Ajay Balankutty, Shih-An Yu, Yiping Feng, Peter R. Kinget:
A 0.6-V Zero-IF/Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications. 538-553 - Wei L. Chan, John R. Long:
A 58-65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply. 554-564 - Mohamed El-Nozahi, Ahmed Amer, Joselyn Torres, Kamran Entesari, Edgar Sánchez-Sinencio:
High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique. 565-577 - Song-Yu Yang, Wei-Zen Chen, Tai-You Lu:
A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology. 578-586 - Chi Fat Chan, Kong-Pang Pun, Ka Nang Leung, Jianping Guo, Lincoln Lai Kan Leung, Oliver Chiu-sing Choy:
A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders. 587-599 - Poki Chen, Chun-Chi Chen, Yu-Han Peng, Kai-Ming Wang, Yu-Shin Wang:
A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of -0.4°C ∼ +0.6°C Over a 0°C to 90°C Range. 600-609 - Yen-Chuan Huang, Tai-Cheng Lee:
A 0.02-mm 2 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology. 610-619 - Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn, Seung-Hoon Lee:
A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp. 620-628 - Afshin Momtaz, Michael M. Green:
An 80 mW 40 Gb/s 7-Tap T/2-Spaced Feed-Forward Equalizer in 65 nm CMOS. 629-639 - Nigel Drego, Anantha P. Chandrakasan, Duane S. Boning:
All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits. 640-651 - Seok-Hoon Kim, Hong-Yun Kim, Young-Jun Kim, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
A 116 fps/74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications. 652-667 - Yu Pu, José de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage. 668-680
Volume 45, Number 4, April 2010
- Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Shiro Dosho, Akira Matsuzawa:
A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator. 697-706 - Yuji Nakajima, Akemi Sakaguchi, Toshio Ohkido, Norihito Kato, Tetsuya Matsumoto, Michio Yotsuyanagi:
A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture. 707-718 - Omid Rajaee, Tawfiq Musah, Nima Maghari, Seiji Takeuchi, Mitsuru Aniya, Koichi Hamashita, Un-Ku Moon:
Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC. 719-730 - Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin:
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure. 731-740 - Eric J. Carlson, Kai Strunz, Brian P. Otis:
A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting. 741-750 - Dinesh Somasekhar, Balaji Srinivasan, Gunjan Pandya, Fatih Hamzaoglu, Muhammad M. Khellah, Tanay Karnik, Kevin Zhang:
Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process. 751-758 - Scott Hanson, Zhiyoong Foo, David T. Blaauw, Dennis Sylvester:
A 0.5 V Sub-Microwatt CMOS Image Sensor With Pulse-Width Modulation Read-Out. 759-767 - Heng-Yu Jian, Zhiwei Xu, Yi-Cheng Wu, Mau-Chung Frank Chang:
A Fractional- PLL for Multiband (0.8-6 GHz) Communications Using Binary-Weighted D/A Differentiator and Offset-Frequency Δ-Σ Modulator. 768-780 - Ping-Hsuan Hsieh, Jay Maxey, Chih-Kong Ken Yang:
A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology. 781-792 - Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou:
187 MHz Subthreshold-Supply Charge-Recovery FIR. 793-803 - Naveen Verma, Ali H. Shoeb, Jose L. Bohorquez, Joel L. Dawson, John V. Guttag, Anantha P. Chandrakasan:
A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System. 804-816 - John Keane, Xiaofei Wang, Devin Persaud, Chris H. Kim:
An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB. 817-829 - Jianjun Yu, Fa Foster Dai, Richard C. Jaeger:
A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 μm CMOS Technology. 830-842 - Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolic:
An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors. 843-855 - Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. 856-862 - Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, Brian Pedersen, Kevin Zhang:
A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m 2 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS. 863-868 - Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno:
A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme. 869-879 - Ki-Whan Song, Jinyoung Kim, Jae-Man Yoon, Sua Kim, Huijung Kim, Hyun-Woo Chung, Hyungi Kim, Kanguk Kim, Hwan-Wook Park, Hyun Chul Kang, Nam-Kyun Tak, Dukha Park, Woo-Seop Kim, Yeong-Taek Lee, Yong Chul Oh, Gyo-Young Jin, Jei-Hwan Yoo, Donggun Park, Kyungseok Oh, Changhyun Kim, Young-Hyun Jun:
A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency. 880-888 - Brian S. Leibowitz, Robert Palmer, John Poulton, Yohan Frans, Simon Li, John M. Wilson, Michael Bucher, Andrew M. Fuller, John G. Eyles, Marko Aleksic, Trey Greer, Nhat Nguyen:
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling. 889-898 - Kangmin Hu, Tao Jiang, Jingguang Wang, Frank O'Mahony, Patrick Yin Chiang:
A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS. 899-908 - Huaide Wang, Jri Lee:
A 21-Gb/s 87-mW Transceiver With FFE/DFE/Analog Equalizer in 65-nm CMOS Technology. 909-920 - Haruya Ishizaki, Masayuki Mizuno:
A 0.2 mm 2 , 27 Mbps 3 mW ADC/FFT-Less FDM BAN Receiver With Energy Exploitation Capability. 921-927 - Toshiya Mitomo, Naoko Ono, Hiroaki Hoshino, Yoshiaki Yoshihara, Osamu Watanabe, Ichiro Seto:
A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications. 928-937
Volume 45, Number 5, May 2010
- Xueyang Geng, Fa Foster Dai, J. David Irwin, Richard C. Jaeger:
24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 μ m SiGe BiCMOS Technology. 944-954 - Ali Afsahi, Arya Behzad, Vikram Magoon, Lawrence E. Larson:
Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2 , ˟ , 2 802.11n MIMO WLAN SoC. 955-966 - Zhiyu Ru, Eric A. M. Klumperink, Carlos E. Saavedra, Bram Nauta:
A 300-800 MHz Tunable Filter and Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver. 967-978 - Francois Rivet, Yann Deval, Jean-Baptiste Bégueret, Dominique Dallet, Philippe Cathelin, Didier Belot:
The Experimental Demonstration of a SASP-Based Full Software Radio Receiver. 979-988 - Tobias D. Werth, Christoph Schmits, Ralf Wunderlich, Stefan Heinen:
An Active Feedback Interference Cancellation Technique for Blocker Filtering in RF Receiver Front-Ends. 989-997 - Usha Gogineni, Hongmei Li, Jesús A. del Alamo, Susan L. Sweeney, Jing Wang, Basanth Jagannathan:
Effect of Substrate Contact Shape and Placement on RF Characteristics of 45 nm Low Power CMOS Devices. 998-1006 - Michiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta:
A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s. 1007-1015 - Imran Ahmed, Jan Mulder, David A. Johns:
A Low-Power Capacitive Charge Pump Based Pipelined ADC. 1016-1027 - Yi-Chuan Tarn, Po-Chih Ku, Hsieh-Hung Hsieh, Liang-Hung Lu:
An Amorphous-Silicon Operational Amplifier and Its Application to a 4-Bit Digital-to-Analog Converter. 1028-1035 - Jinn-Shyan Wang, Chun-Yuan Cheng, Je-Ching Liu, Yu-Chia Liu, Yi-Ming Wang:
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop. 1036-1047 - Davide De Caro, Carlo Alberto Romani, Nicola Petra, Antonio G. M. Strollo, Claudio Parrella:
A 1.27 GHz, All-Digital Spread Spectrum Clock Generator/Synthesizer in 65 nm CMOS. 1048-1060 - Mohamed M. Elsayed, Edgar Sánchez-Sinencio:
A Low THD, Low Power, High Output-Swing Time-Mode-Based Tunable Oscillator Via Digital Harmonic-Cancellation Technique. 1061-1071 - Hsin-Ta Wu, Ruonan Han, Wuttichai Lerdsitsomboon, Changhua Cao, Kenneth K. O:
Multi-Level Amplitude Modulation of a 16.8-GHz Class-E Power Amplifier With Negative Resistance Enhanced Power Gain for 400-Mbps Data Transmission. 1072-1079 - Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida:
Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs. 1080-1087
Volume 45, Number 6, June 2010
- Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa:
A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS. 1091-1098 - Ali Agah, Katelijn Vleugels, Peter B. Griffin, Mostafa Ronaghi, James D. Plummer, Bruce A. Wooley:
A High-Resolution Low-Power Incremental Sigma Delta ADC With Extended Range for Biosensor Arrays. 1099-1110 - Yan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti:
A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. 1111-1121 - Cho-Ying Lu, Jose Fabian Silva-Rivas, Praveena Kode, José Silva-Martínez, Sebastian Hoyos:
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth. 1122-1136 - Wei-Hao Chiu, Yu-Hsiang Huang, Tsung-Hsien Lin:
A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops. 1137-1149 - Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho:
An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback. 1150-1158 - Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx:
A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS. 1159-1171 - Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz:
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber. 1172-1185 - Byungsub Kim, Vladimir Stojanovic:
An Energy-Efficient Equalized Transceiver for RC-Dominant Channels. 1186-1197 - Lynn Bos, Gerd Vandersteen, Pieter Rombouts, Arnd Geis, Alonso Morgado, Yves Rolain, Geert Van der Plas, Julien Ryckaert:
Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS. 1198-1208 - Patrick P. Mercier, Manish Bhardwaj, Denis C. Daly, Anantha P. Chandrakasan:
A Low-Voltage Energy-Sampling IR-UWB Digital Baseband Employing Quadratic Correlation. 1209-1219 - Bart R. Zeydel, Dursun Baran, Vojin G. Oklobdzija:
Energy-Efficient Design Methodologies: High-Performance VLSI Adders. 1220-1233 - Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Yung-Chi Chen,