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ORCIDFrancisco José Ballester-Merelo
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2020 – today
- 2021
[j5]Raúl Esteve Bosch
, José F. Toledo Alarcón, Vicente Herrero-Bosch, Ander Simón Estévez, Francesc Monrabal Capilla, Vicente Álvarez Puerta, Javier Rodríguez Samaniego, Marc Querol Segura, Francisco José Ballester-Merelo:
The Event Detection System in the NEXT-White Detector. Sensors 21(2): 673 (2021)- [j4]Nieves Gallego Ripoll, Luís Enrique Gómez Aguilera, Ferran Mocholí Belenguer, Antonio Mocholí Salcedo, Francisco José Ballester-Merelo:
Design, Implementation, and Configuration of Laser Systems for Vehicle Detection and Classification in Real Time. Sensors 21(6): 2082 (2021)
2010 – 2019
- 2018
- [j3]Melisa Acosta-Coll, Francisco José Ballester-Merelo, Marcos Martínez-Peiró, Emiro De la Hoz-Franco:
Real-Time Early Warning System Design for Pluvial Flash Floods - A Review. Sensors 18(7): 2255 (2018)
2000 – 2009
- 2008
- [j2]Armando Mora Campos, Francisco José Ballester-Merelo, Marcos Martínez Peiró, José A. Canals Esteve:
Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management. Microprocess. Microsystems 32(2): 68-78 (2008) - 2004
- [j1]Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró:
Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. Microprocess. Microsystems 28(9): 509-518 (2004) - [c6]Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer:
FPGA Custom DSP for ECG Signal Analysis and Compression. FPL 2004: 954-958 - [c5]Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá:
Architectures for ICT on FPGA. FPT 2004: 403-406 - [c4]Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá:
2D-DCT on FPGA by polynomial transformation in two-dimensions. ISCAS (3) 2004: 365-368 - 2003
- [c3]Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Francisco José Mora Mas:
Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. FPL 2003: 533-542 - [c2]Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco José Ballester-Merelo, Vicente Herrero-Bosch, Joaquín Cerdá:
A new inverse discrete wavelet packet transform architecture. ISSPA (2) 2003: 443-446 - 2000
- [c1]Rafael Gadea Gironés, Joaquín Cerdá, Francisco José Ballester-Merelo, Antonio Mocholí Salcedo:
Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. ISSS 2000: 225-230
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