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2020 – today
- 2021
[j4]Chunhua Yao, Xinyu Song, Xuelei Zhang, Weicheng Zhao, Ao Feng
:
Multitask Learning for Aspect-Based Sentiment Classification. Sci. Program. 2021: 2055555:1-2055555:9 (2021)
2010 – 2019
- 2019
- [j3]Hongyi Gao, Xi Zeng, Chunhua Yao:
Application of improved distributed naive Bayesian algorithms in text classification. J. Supercomput. 75(9): 5831-5847 (2019) - 2013
- [c7]Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao:
Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems. VLSI Design 2013: 25-30 - 2011
- [j2]Chunhua Yao, Kewal K. Saluja, Parmesh Ramanathan:
Calibrating On-chip Thermal Sensors in Integrated Circuits: A Design-for-Calibration Approach. J. Electron. Test. 27(6): 711-721 (2011) - [j1]Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2): 317-322 (2011) - [c6]Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Temperature Dependent Test Scheduling for Multi-core System-on-Chip. Asian Test Symposium 2011: 27-32 - [c5]Krishna Bharath, Chunhua Yao, Nam Sung Kim, Parameswaran Ramanathan, Kewal K. Saluja:
A low cost approach to calibrate on-chip thermal sensors. ISQED 2011: 572-576 - [c4]Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Thermal-Aware Test Scheduling Using On-chip Temperature Sensors. VLSI Design 2011: 376-381
2000 – 2009
- 2009
- [c3]Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies. Asian Test Symposium 2009: 281-286 - [c2]Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
Power and thermal constrained test scheduling. ITC 2009: 1 - [c1]Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar:
WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. VLSI Design 2009: 479-484
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